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1. 发明专利

JP2010146514A Information processor and neural network circuit using the same 有权
标题翻译：信息处理器和使用相同的神经网络电路
公开(公告)号：JP2010146514A
公开(公告)日：2010-07-01
申请号：JP2008326313
申请日：2008-12-22
申请人： Takashi Morie , Sharp Corp , シャープ株式会社 , 隆森江
发明人： ONISHI SHIGEO , MORIE TAKASHI
IPC分类号： G06G7/60 , G06N3/063
CPC分类号： G11C11/54 , G06N3/063 , G11C13/0002
摘要： PROBLEM TO BE SOLVED: To provide an information processor storing synapse bond strength as an analog quantity without increasing an occupied area on an LSI chip by indicating the synapse bond strength using a resistance value of a resistance variable memory element. SOLUTION: The information processor 100 includes at least one synapse circuit 102. The synapse circuit 102 has the resistance variable memory element 24 reversibly varied by the application of voltage pulses, and an STDP (spike-timing dependent synaptic plasticity) section 25 carrying out operation using a function that indicates a preset nonlinear voltage waveform according to a lag of input timing between two spike pulses input at different timing. The STDP section 25 carries out operation to the lag of the input timing when the two spike pulses are input, and sets a voltage pulse applied to the resistance variable memory element 24 based on the operation result. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过使用电阻可变存储元件的电阻值指示突触结合强度，提供将突触结合强度作为模拟量存储的信息处理器，而不增加LSI芯片上的占用面积。解决方案：信息处理器100包括至少一个突触电路102.突触电路102具有通过施加电压脉冲而可逆地变化的电阻可变存储元件24，以及STDP（尖峰定时依赖性突触可塑性）部分25 根据在不同定时输入的两个尖峰脉冲之间的输入定时的滞后，使用表示预设非线性电压波形的功能进行操作。当输入两个尖峰脉冲时，STDP部25进行输入定时的滞后运算，根据运算结果设定施加到电阻变量存储元件24的电压脉冲。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009282782A Product arithmetic unit including resistance change type variable resistor element, product sum arithmetic unit, neural network providing each neuron element with these arithmetic units, and product arithmetic method 有权
标题翻译：产品算术单元，包括电阻变化型变量电阻元件，产品单位算术单元，提供每个具有这些算术单位的神经元元素的神经网络和产品算术方法
公开(公告)号：JP2009282782A
公开(公告)日：2009-12-03
申请号：JP2008134682
申请日：2008-05-22
申请人： Takashi Morie , Sharp Corp , シャープ株式会社 , 隆森江
发明人： ONISHI SHIGEO , ISHIHARA KAZUYA , MORIE TAKASHI
IPC分类号： G06N3/063
摘要： PROBLEM TO BE SOLVED: To simplify configurations of a product arithmetic unit and a product sum arithmetic unit and to reduce occupied areas of the product arithmetic unit and the product sum arithmetic unit in the area of the whole circuit including these units. SOLUTION: When a single voltage pulse of pulse width Ti corresponding to a multiplicand is input to a terminal A of the resistance change type variable resistor element 1 having terminals A, B and a voltage pulse string of a pulse frequency Fi corresponding to a multiplier is input to the terminal B, a PWM (pulse width modulation) signal according to the Fi, Ti corresponding to a product operation result between the multiplicand and the multiplier is output. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了简化产品运算单元和乘积和运算单元的配置，并且在包括这些单元的整个电路的区域中减少乘积运算单元和乘积和运算单元的占用面积。解决方案：当对应于被乘数的脉冲宽度Ti的单个电压脉冲被输入到具有端子A，B的电阻变化型可变电阻器元件1的端子A和与之相对应的脉冲频率Fi的电压脉冲串时向终端B输入乘法器，输出与乘法器和乘法器之间的乘积运算结果对应的根据Fi，Ti的PWM（脉宽调制）信号。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2008306157A Variable resistive element and method for manufacturing the same, and nonvolatile semiconductor storage device 有权
标题翻译：可变电阻元件及其制造方法以及非易失性半导体存储器件
公开(公告)号：JP2008306157A
公开(公告)日：2008-12-18
申请号：JP2007292763
申请日：2007-11-12
申请人： National Institute Of Advanced Industrial & Technology , Sharp Corp , シャープ株式会社 , 独立行政法人産業技術総合研究所
发明人： TAMAI YUKIO , HOSOI YASUNARI , AWAYA NOBUYOSHI , ONISHI SHIGEO , ISHIHARA KAZUYA , SHIMA HISASHI , TAKANO FUMIYOSHI , AKINAGA HIROYUKI
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0011 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/51 , G11C2213/56 , G11C2213/77 , H01L27/101 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： PROBLEM TO BE SOLVED: To provide a variable resistive element which performs high speed and low power consumption operation. SOLUTION: In the variable resistive element, a metal oxide layer 10 is provided between a first electrode 11 and a second electrode 12, and electrical resistance between the first and the second electrodes reversibly varies in accordance with application of electrical stress to between the first and the second electrodes. The metal oxide layer 10 has a filament 13 which is a current path wherein the density of a current flowing between the first and the second electrodes locally increases. A portion including at least the vicinity of an interface, which is between at least the one specified electrode 11 between the first electrode and the second electrode and the filament 13, on an interface between the specified electrode 11 and the metal oxide layer 10 is provided with an interface oxide 15 which is an oxide of at least one element included in the specified electrode 11 and different from the oxide of the metal oxide layer 10. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种执行高速和低功耗操作的可变电阻元件。解决方案：在可变电阻元件中，金属氧化物层10设置在第一电极11和第二电极12之间，并且第一和第二电极之间的电阻根据电应力的应用而可逆地变化，第一和第二电极。金属氧化物层10具有灯丝13，其是电流路径，其中在第一和第二电极之间流动的电流的密度局部增加。在规定的电极11和金属氧化物层10之间的界面上，至少包括位于第一电极和第二电极之间的至少一个规定电极11与灯丝13之间的界面附近的部分具有界面氧化物15，其是包括在指定电极11中并且不同于金属氧化物层10的氧化物的至少一种元素的氧化物。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008146711A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008146711A
公开(公告)日：2008-06-26
申请号：JP2006330045
申请日：2006-12-06
申请人： Sharp Corp , シャープ株式会社
发明人： INOUE TAKESHI , HOSOI YASUNARI , ONISHI SHIGEO , AWAYA NOBUYOSHI
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which can execute individually and simultaneously re-writing operation in which resistance variation is different for a plurality of memory cells provided with a variable resistance element of which the resistance property is varied by applying voltage. SOLUTION: The nonvolatile semiconductor memory device is provided with a load resistance property variable circuit 14 constituted so that either of two load resistance properties can be selected individually in accordance with difference of first re-writing operation transiting the resistance property of the variable resistance element to be re-written from a low resistance state to a high resistance state and second re-writing operation transiting it from a high resistance state to a low resistance state for each of bit lines BL0 to 3 connected commonly to the memory cells of the same column, and a re-writing voltage pulse applying circuit 13a applying a first voltage pulse to be applied in the first re-writing operation and a second voltage pulse to be applied in the second re-writing operation to the memory cell to be re-written through load resistance property variable circuit 14 and the bit lines BL0 to 3. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种非易失性半导体存储器件，其可以对设置有电阻特性变化的可变电阻元件的多个存储单元单独地并且同时重写电阻变化不同的重写操作通过施加电压。解决方案：非易失性半导体存储器件设置有负载电阻特性可变电路14，该负载电阻属性可变电路14构成为可以根据经过变量的电阻特性的第一重写操作的差分别选择两种负载电阻特性中的任一种电阻元件从低电阻状态重写到高电阻状态，并且第二重写操作将其从高电阻状态转移到低电阻状态，用于与每个连接到存储器单元的存储器单元的位线BL0至3 相同的列，以及施加在第一重写操作中施加的第一电压脉冲的再写入电压脉冲施加电路13a和将要在第二重写操作中施加的第二电压脉冲作为存储单元通过负载电阻特性可变电路14和位线BL0〜3重新写入。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JPH11274287A Method of forming element isolating region 失效
标题翻译：形成元素分离区域的方法
公开(公告)号：JPH11274287A
公开(公告)日：1999-10-08
申请号：JP7531598
申请日：1998-03-24
申请人： Sharp Corp , シャープ株式会社
发明人： DOI TSUKASA , ONISHI SHIGEO , IGUCHI KATSUJI , NIIMURA NAOYUKI
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： PROBLEM TO BE SOLVED: To obtain a good burying characteristic up to fine element isolating regions without having the ground dependence, by burying an insulation film in trenches in the condition of forming the trenches utilizing ozone-TEOS reaction.
SOLUTION: A pad oxide film 2 and Si nitride film 3 are formed on a semiconductor substrate 1, trenches are formed into the semiconductor substrate 1 by anisotropically etching them. A first oxide film 4 is buried on the inner surfaces of the trenches, and a second oxide film 5 is buried in the trenches with the surface above the semiconductor substrate 1 surface. By heat treatment, the mass of the ozone-TEOS film 4 is compacted, and the surface of the second oxide film 5 is planarized and thermally oxidized to form a re-oxide film 6 below the second oxide film 5, and the pad oxide film 2 and Si nitride film 3 are removed to form element isolating regions.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：通过在形成使用臭氧-TEOS反应形成沟槽的条件下，通过在沟槽中埋入绝缘膜，获得良好的掩埋特性，直到细小的元件隔离区域而不具有地面依赖性。解决方案：在半导体衬底1上形成衬垫氧化膜2和氮化硅膜3，通过各向异性蚀刻沟槽，形成半导体衬底1中的沟槽。第一氧化物膜4被埋在沟槽的内表面上，并且第二氧化膜5被埋在具有半导体衬底1表面上方的表面的沟槽中。通过热处理，臭氧-TEOS膜4的质量被压实，并且第二氧化物膜5的表面被平坦化并热氧化，以在第二氧化膜5下方形成再氧化膜6，并且衬垫氧化膜 2和氮化硅膜3被去除以形成元件隔离区域。

6. 发明专利

JP2010103555A Variable resistor element 有权
标题翻译：可变电阻元件
公开(公告)号：JP2010103555A
公开(公告)日：2010-05-06
申请号：JP2009296280
申请日：2009-12-25
申请人： National Institute Of Advanced Industrial Science & Technology , Sharp Corp , シャープ株式会社 , 独立行政法人産業技術総合研究所
发明人： TAMAI YUKIO , HOSOI YASUNARI , AWAYA NOBUYOSHI , ONISHI SHIGEO , ISHIHARA KAZUYA , SHIMA HISASHI , TAKANO FUMIYOSHI , AKINAGA HIROYUKI
IPC分类号： H01L49/00 , H01L27/10 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To reduce a forming voltage applied to form a through-hole in a metal oxide material, without making the leakage current increase. SOLUTION: A variable resistor 1 includes an electrode 11, an electrode 12, and a metal oxide material disposed in between the electrode 11 and electrode 12, and the electrical resistance for the variable resistor 1 between the electrode 11 and the electrode 12 varies reversibly, according to the voltage applied between the electrode 11 and the electrode 12. The metal oxide material includes a resistor 14, which is separated from at least either of the electrode 11 and the electrode 12 and has resistance lower than resistance of the metal oxide material. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了降低施加在金属氧化物材料中形成通孔的成形电压，而不会使漏电流增加。解决方案：可变电阻器1包括设置在电极11和电极12之间的电极11，电极12和金属氧化物材料，以及电极11和电极12之间的可变电阻器1的电阻根据施加在电极11和电极12之间的电压可逆地变化。金属氧化物材料包括与电极11和电极12中的至少一个分离的电阻器14，并且具有低于金属电阻的电阻氧化物。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2009141225A Variable resistive element, method for manufacturing variable resistive element, nonvolatile semiconductor storage device 审中-公开
标题翻译：可变电阻元件，制造可变电阻元件的方法，非易失性半导体存储器件
公开(公告)号：JP2009141225A
公开(公告)日：2009-06-25
申请号：JP2007317733
申请日：2007-12-07
申请人： National Institute Of Advanced Industrial & Technology , Sharp Corp , シャープ株式会社 , 独立行政法人産業技術総合研究所
发明人： TAMAI YUKIO , HOSOI YASUNARI , AWAYA NOBUYOSHI , ONISHI SHIGEO , ISHIHARA KAZUYA , SHIMA HISASHI , TAKANO FUMIYOSHI , AKINAGA HIROYUKI
IPC分类号： H01L27/10 , G11C13/00 , H01L45/00 , H01L49/00
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0028 , G11C2013/0083 , G11C2213/32 , G11C2213/56 , G11C2213/77 , H01C7/108 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1658 , Y10T29/49082
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device using a variable resistive element which lowers a forming voltage for forming a conduction portion within a metal oxide without increasing a leak current. SOLUTION: A variable resistive element 1 includes: an electrode 11, an electrode 12, and a metal oxide 10 interposed between the electrode 11 and the electrode 12, wherein the electrical resistance between the electrode 11 and the electrode 12 varies according to an applied voltage to the electrode 11 and the electrode 12, and a low resistance object 14, the electrical resistance of which is lower than that of the metal oxide 10, and isolated from at least one of the electrode 11 and the electrode 12, is provided in the metal oxide 10. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用可变电阻元件的非易失性半导体存储装置，其可降低用于在金属氧化物内形成导电部分的形成电压，而不增加泄漏电流。解决方案：可变电阻元件1包括：电极11，电极12和介于电极11和电极12之间的金属氧化物10，其中电极11和电极12之间的电阻根据对电极11和电极12施加的电压以及电阻低于金属氧化物10并与电极11和电极12中的至少一个隔离的低电阻对象14是提供在金属氧化物10中。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2006196516A Process for fabricating semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：JP2006196516A
公开(公告)日：2006-07-27
申请号：JP2005003799
申请日：2005-01-11
申请人： Sharp Corp , シャープ株式会社
发明人： NIIMURA NAOYUKI , ONISHI SHIGEO , ONISHI TETSUYA , YAMAZAKI NOBUO , SHIBUYA TAKAHIRO , NAKANO TAKASHI , TAJIRI MASAYUKI
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/10
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor memory device of cross point structure having homogeneous crystallinity as a storage material for storing data.
SOLUTION: The process for fabricating a semiconductor memory device provided with a plurality of upper electrode interconnect lines T extending in the same direction and a plurality of lower electrode interconnect lines B extending in the direction intersecting the extending direction of the upper electrode interconnect lines T perpendicularly, and having a cross point structure obtained by forming a storage material for storing data between the upper electrode interconnect lines T and the lower electrode interconnect lines B comprises a step for forming a plurality of lower electrode interconnect lines B by smoothing the plurality of lower electrode interconnect lines B and an insulating film deposited on the opposite sides thereof to have a uniform flush plane, a step for depositing a storage material film becoming the storage material on the plurality of lower electrode interconnect lines B, and a step for performing annealing by heat treatment between the lower electrode interconnect line forming step and the storage material film depositing step and recovering damage due to polishing on the surface of the lower electrode interconnect line B.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造具有均匀结晶度的交叉点结构的半导体存储器件作为用于存储数据的存储材料的工艺。解决方案：制造半导体存储器件的方法，该半导体存储器件具有沿相同方向延伸的多个上电极互连线T和沿与上电极互连的延伸方向相交的方向延伸的多个下电极互连线B 具有通过形成用于在上部电极布线T和下部电极布线B之间存储数据的存储材料而获得的交叉点结构的线T包括通过平滑多个下部电极布线B而形成多个下部电极布线B的步骤的下电极布线B和沉积在其相对侧上的绝缘膜以具有均匀的齐平面;用于在多个下电极布线B上沉积成为存储材料的存储材料膜的步骤，以及用于执行在下电极interco之间进行热处理退火连接线形成步骤和存储材料膜沉积步骤，并且在下电极互连线B的表面上恢复由于抛光引起的损伤。版权所有（C）2006，JPO和NCIPI

9. 发明专利

JP2006147694A Structure and manufacturing method of semiconductor storage device 有权
标题翻译：半导体存储器件的结构与制造方法
公开(公告)号：JP2006147694A
公开(公告)日：2006-06-08
申请号：JP2004333130
申请日：2004-11-17
申请人： Sharp Corp , シャープ株式会社
发明人： ONISHI TETSUYA , NIIMURA NAOYUKI , YAMAZAKI NOBUO , SHIBUYA TAKAHIRO , NAKANO TAKASHI , TAJIRI MASAYUKI , ONISHI SHIGEO
IPC分类号： H01L27/105 , H01L43/08
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device of a memory cell area smaller than a minimum memory cell area specified by a minimum processing size on a manufacturing process by using the smaller number of photographing processes, and to provide a method of manufacturing the semiconductor storage device.
SOLUTION: The semiconductor storage device of a cross-point structure provided with a plurality of upper electrodes 2 extending in the same direction and a plurality of lower electrodes 1 extending in a direction crossing orthogonally the extending direction of the upper electrodes 2 to form a storage material for accumulating data in layers between the upper electrodes 2 and the lower electrodes 1. The storage material is formed of a perovskite material, and formed to extend along the upper electrodes 2 to the side of the lower electrodes 1 of the respective upper electrodes 2.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种存储单元区域的半导体存储装置，该存储单元区域小于通过使用较少数量的拍摄处理在制造过程中由最小处理尺寸指定的最小存储单元区域，并且提供一种方法制造半导体存储装置。解决方案：提供具有沿相同方向延伸的多个上电极2的交叉点结构的半导体存储装置和沿与上电极2的延伸方向垂直交叉的方向延伸的多个下电极1至形成用于在上部电极2和下部电极1之间层叠数据的存储材料。储存材料由钙钛矿材料形成，并且形成为沿着上部电极2向相应的上部电极2和下部电极1的下部电极1的侧面延伸上电极2.版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005303323A Etching method of ferroelectric film 审中-公开
标题翻译：电磁膜蚀刻方法
公开(公告)号：JP2005303323A
公开(公告)日：2005-10-27
申请号：JP2005143279
申请日：2005-05-16
申请人： Sharp Corp , シャープ株式会社
发明人： ONISHI SHIGEO , KUDO ATSUSHI , SAKIYAMA KEIZO , URASHIMA HITOSHI
IPC分类号： H01L21/3065 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To perform microfabrication of a ferroelectric film at a high etching rate which is free from a dimensional shift and higher in accuracy.
SOLUTION: A PZT film 6 is formed on a Pt film 5 by a sol-gel method, and an SOG film 8 used as a mask is patterned on the PZT film 6. Its sample wafer is placed in an ECR plasma etching system. Mixed gas of Ar gas and chlorine gas as an etching gas is introduced so that a flow rate ratio of halogen gas to the total flow rate of the mixed gas may become ≤50%. The PZT film 6 is etched in the range of a substrate temperature of ≥100°C but ≤400°C.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：以高刻蚀速率进行铁电薄膜的微细加工，其没有尺寸偏移并且精度更高。解决方案：通过溶胶 - 凝胶法在Pt膜5上形成PZT膜6，在PZT膜6上图案化用作掩模的SOG膜8.将样品晶片置于ECR等离子体蚀刻系统。引入作为蚀刻气体的Ar气体和氯气的混合气体，使得卤素气体与混合气体的总流量的流量比可以变为≤50％。 PZT膜6在衬底温度≥100℃但≤400℃的范围内被蚀刻。版权所有（C）2006，JPO＆NCIPI

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