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    • 4. 发明授权
    • Power module
    • 电源模块
    • US08254133B2
    • 2012-08-28
    • US12663813
    • 2008-06-12
    • Makoto Imai
    • Makoto Imai
    • H05K1/14
    • H01L25/072H01L23/04H01L23/473H01L24/48H01L25/16H01L2224/48091H01L2224/48108H01L2224/48157H01L2224/48464H01L2924/00014H01L2924/01079H01L2924/1305H01L2924/13055H01L2924/1815H01L2924/19041H01L2924/19107H01L2924/00H01L2224/45099H01L2224/45015H01L2924/207
    • Provided is a power module capable of welding a snubber capacitor without causing melting damage to a resin housing by welding heat. When leads of a snubber capacitor are respectively welded to upper surfaces of the specific portions of a P-pole bus bar and an N-pole bus bar, the welding heat generated at the specific portions of the P-pole bus bar and the N-pole bus bar is respectively radiated from openings, through which the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar are exposed. As a result, the snubber capacitor can be later appended by welding without causing melting damage to the resin housing due to the welding heat. During welding, a separate cooling head is inserted into the openings to forcibly cool the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar respectively, so that the melting damage to a resin housing can be more reliably avoided.
    • 提供了能够焊接缓冲电容器而不会通过焊接热而对树脂壳体造成熔融损伤的电力模块。 当缓冲电容器的引线分别焊接在P极母线和N极母线的特定部分的上表面时,在P极母线和N极母线的特定部分产生的焊接热, 极母线从开口分别辐射,P极母线和N极母线的特定部分的下表面露出。 结果,缓冲电容器可以随后通过焊接而附加,而不会由于焊接热而对树脂壳体造成熔融损坏。 在焊接过程中,将一个单独的冷却头插入开口,以分别强制地冷却P极汇流条和N极汇流条的特定部分的下表面,使得对树脂外壳的熔化损伤可以更多 可靠地避免。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20150295489A1
    • 2015-10-15
    • US14443532
    • 2012-12-25
    • Makoto IMAI
    • Makoto Imai
    • H02M1/32H02M3/337H01L23/528H01L27/06H01L23/525
    • H02M1/32H01L23/5256H01L23/528H01L27/0629H02M3/158H02M3/337H02M2001/325
    • A semiconductor device presented herein includes a first wiring including a first end and a second end configured to receive a voltage lower than a voltage of the first end. The semiconductor device includes a second wiring including a third end connected to the first end, and a fourth end connected to the second end. The semiconductor device includes a switching element set on the first wiring, a capacitor set on the second wiring, and a fuse portion set on the second wiring and positioned on a third end side of the capacitor. The semiconductor device includes a potential sensing portion connected to the second wiring between the fuse portion and the capacitor and configured to sense a potential of a connection point thereof.
    • 本文提出的半导体器件包括第一布线,其包括第一端和被配置为接收低于第一端的电压的电压的第二端。 半导体器件包括第二布线,其包括连接到第一端的第三端和连接到第二端的第四端。 半导体器件包括设置在第一布线上的开关元件,设置在第二布线上的电容器和设置在第二布线上且位于电容器的第三端侧的熔丝部分。 半导体器件包括电位检测部分,其连接到熔丝部分和电容器之间的第二布线,并被配置为感测其连接点的电位。
    • 10. 发明申请
    • Semiconductor device and multilayer semiconductor device
    • 半导体器件和多层半导体器件
    • US20120025391A1
    • 2012-02-02
    • US13067660
    • 2011-06-17
    • Makoto Imai
    • Makoto Imai
    • H01L23/48
    • H01L23/544G11C8/12G11C16/20H01L24/16H01L24/17H01L25/0657H01L2223/5444H01L2224/16145H01L2224/17181H01L2225/06513
    • Disclosed herein is a semiconductor device including: an input terminal receiving, if a preceding-stage semiconductor device is layered on a predetermined one of an upper layer and a lower layer, a bit train outputted from the preceding-stage semiconductor device; a semiconductor device identifier hold block holding a semiconductor device identifier for uniquely identifying the semiconductor device; a semiconductor device identifier computation block executing computation by using the semiconductor device identifier to update the semiconductor device identifier held in the semiconductor device identifier hold block according to a result of the computation; a control block once holding data of a bit train entered from the input terminal to control updating of the semiconductor device identifier executed by the semiconductor device identifier computation block based on the held data; and an output terminal outputting the bit train held in the control block to a succeeding-stage semiconductor device layered on another layer.
    • 这里公开了一种半导体器件,包括:输入端子,如果前级半导体器件层叠在上层和下层的预定的一层上,则从前级半导体器件输出的位串; 保持用于唯一地识别半导体器件的半导体器件标识符的半导体器件标识符保持块; 半导体器件标识符计算块,通过使用半导体器件标识符,根据计算结果来更新保持在半导体器件标识符保持块中的半导体器件识别符,执行计算; 一个控制块,一旦保持从输入端输入的位串的数据,以控制由半导体器件标识符计算块执行的半导体器件标识符的更新,基于所保持的数据; 以及输出端子,将保持在控制块中的位串输出到分层在另一层上的后级半导体器件。