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    • 1. 发明授权
    • Bipolar logic circuit having two multi-emitter transistors with an
emitter of one connected to the collector of the other to prevent
saturation
    • 双极逻辑电路具有两个多发射极晶体管,其发射极连接到另一个的集电极以防止饱和
    • US4697102A
    • 1987-09-29
    • US737872
    • 1985-05-28
    • Takahiro OkabeMakoto HayashiKatuhiro MorisuyeTomoyuki WatanabeKatsuyoshi WashioSetsuo OguraMakoto FurihataShizuo Kondo
    • Takahiro OkabeMakoto HayashiKatuhiro MorisuyeTomoyuki WatanabeKatsuyoshi WashioSetsuo OguraMakoto FurihataShizuo Kondo
    • H03K19/00H03K19/013H03K19/082
    • H03K19/001H03K19/013
    • A logic circuit is provided which includes a first multi-emitter transistor with its emitters coupled to a group of first input lines and a first transistor with its base coupled to the collector of said first multi-emitter transistor. A second transistor is also provided with its base coupled to the collector of said first transistor, said second transistor having a polarity opposite to that of said first multi-emitter transistor. A second multi-emitter transistor is connected with its base coupled to the collector of said second transistor and with its emitters coupled to a group of second input lines, and a third transistor is connected with its base coupled to the collector of said second multi-emitter transistor and with its collector coupled to an output line. The collector of said first multi-emitter transistor is coupled to the emitter of said second multi-emitter transistor in order to absorb minority carriers stored in the transistors. This feature significantly improves the circuit operating speed. A further feature is the provision of a logic circuit which is highly integrated and which consumes reduced amounts of electric power, while maintaining high-speed performance of the TTL circuit, by substituting a multi-collector transistor that reversely operates for an inverter portion of the TTL circuit.
    • 提供了一种逻辑电路,其包括第一多发射极晶体管,其发射极耦合到一组第一输入线,第一晶体管的基极耦合到所述第一多发射极晶体管的集电极。 第二晶体管还设置有其基极耦合到所述第一晶体管的集电极,所述第二晶体管具有与所述第一多发射极晶体管的极性相反的极性。 第二多发射极晶体管与其基极耦合,耦合到所述第二晶体管的集电极,并且其发射极耦合到一组第二输入线,并且第三晶体管与其基极连接,耦合到所述第二多晶体管的集电极, 发射极晶体管,其集电极耦合到输出线。 所述第一多发射极晶体管的集电极耦合到所述第二多发射极晶体管的发射极,以便吸收存储在晶体管中的少数载流子。 该功能显着提高了电路工作速度。 另一个特征是提供了一种高度集成的逻辑电路,并且通过将反向工作的多集电极晶体管替换为逆变器部分的多集电极晶体管,同时维持TTL电路的高速性能,从而消耗了较少的电功率 TTL电路。
    • 2. 发明授权
    • Logic circuit
    • 逻辑电路
    • US4670859A
    • 1987-06-02
    • US704412
    • 1985-02-22
    • Makoto FurihataSetsuo OguraShizuo KondoEiji Minamimura
    • Makoto FurihataSetsuo OguraShizuo KondoEiji Minamimura
    • G11C17/00H03K19/00H03K19/091
    • H03K19/091H03K19/001
    • A logic circuit of a large scale which consumes small amounts of electric power is comprised of a plurality of ROM portions each formed of IIL circuits. Input signal lines are commonly used to transmit input signals to the ROM portions. The plurality of ROM portions are selectively operated by ROM select signals, and outputs corresponding to the input signals are obtained from a selected ROM portion. To select a particular ROM portion out of the plurality of ROM portions, the emitters of inverse npn transistors of IIL circuits constituting the selected ROM portion are rendered to assume ground potential. In the meantime, the emitters of the inverse npn transistors of IIL circuits in the non-selected ROM portions are held in a floating condition. This makes it possible to obtain a logic circuit which consumes small amounts of electric power with a very simple construction since the non-selected ROM portions consume no power.
    • 消耗少量电力的大规模的逻辑电路包括由IIL电路形成的多个ROM部分。 输入信号线通常用于将输入信号发送到ROM部分。 多个ROM部分由ROM选择信号选择性地操作,并且从所选择的ROM部分获得对应于输入信号的输出。 为了选择多个ROM部分中的特定ROM部分,构成所选择的ROM部分的IIL电路的逆npn晶体管的发射极被呈现为地电位。 同时,未选择的ROM部分中的IIL电路的逆npn晶体管的发射极保持在浮置状态。 这使得可以以非常简单的结构获得消耗少量电力的逻辑电路,因为未选择的ROM部分不消耗电力。