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1. 发明申请

US20080024206A1 Noise reduction circuit 有权
标题翻译：降噪电路
公开(公告)号：US20080024206A1
公开(公告)日：2008-01-31
申请号：US11826582
申请日：2007-07-17
申请人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
发明人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
IPC分类号： H03K5/00
CPC分类号： H03K5/1252 , H04N5/21
摘要： A noise reduction circuit receives, as an input signal, a voltage difference between two different signals. The noise reduction circuit includes: an amplifier circuit for amplifying the two different signals; a voltage difference detection circuit for detecting a voltage difference between the two different signals amplified by the amplifier circuit; and an electric charge accumulation circuit section or a voltage adding circuit. The electric charge accumulation circuit section accumulates, a predetermined number of times, an electric charge corresponding to the voltage difference detected by the voltage difference detection circuit and combines the accumulated electric charges to output the resultant electric charge. The voltage adding circuit adds, a predetermined number of times, the voltage difference detected by the voltage difference detection circuit.
摘要翻译：噪声降低电路作为输入信号接收两个不同信号之间的电压差。噪声降低电路包括：用于放大两个不同信号的放大器电路; 用于检测由放大器电路放大的两个不同信号之间的电压差的电压差检测电路; 和电荷累积电路部分或电压相加电路。电荷累积电路部分累积与由电压差检测电路检测出的电压差对应的电荷的预定次数，并组合累计的电荷以输出所得的电荷。电压加法电路将电压差检测电路检测出的电压差加上规定次数。

2. 发明授权

US07589585B2 Noise reduction circuit 有权
标题翻译：降噪电路
公开(公告)号：US07589585B2
公开(公告)日：2009-09-15
申请号：US11826582
申请日：2007-07-17
申请人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
发明人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
IPC分类号： H03K17/16 , H03K5/00
CPC分类号： H03K5/1252 , H04N5/21
摘要： A noise reduction circuit outputs a signal corresponding to a voltage difference between two different signals. The noise reduction circuit includes: an amplifier circuit for amplifying the two different signals at different timings; and a voltage difference detection circuit for detecting a voltage difference between the two different signals amplified by the amplifier circuit. The noise reduction circuit accumulates, a predetermined number of times, an electric charge corresponding to the voltage difference detected by the voltage difference detection circuit and combines the accumulated electric charges to output a resultant electric charge.
摘要翻译：噪声降低电路输出与两个不同信号之间的电压差对应的信号。噪声降低电路包括：放大器电路，用于在不同的定时放大两个不同的信号; 以及电压差检测电路，用于检测由放大器电路放大的两个不同信号之间的电压差。噪声降低电路以预定次数累积与由电压差检测电路检测出的电压差对应的电荷，并组合累积的电荷以输出所得的电荷。

3. 发明申请

US20060095975A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060095975A1
公开(公告)日：2006-05-04
申请号：US11212585
申请日：2005-08-29
申请人： Takayoshi Yamada , Shinzo Koyama , Yoshihisa Kato , Yasuhiro Shimada
发明人： Takayoshi Yamada , Shinzo Koyama , Yoshihisa Kato , Yasuhiro Shimada
IPC分类号： H04L9/32
CPC分类号： G06F21/79 , H04L9/085
摘要： A semiconductor device of the present invention includes: at least one of non-volatile memory unit operable to store data; at least one of an arithmetic-logic unit operable to perform an arithmetic-logic operation using data which is stored in the memory unit and data that is inputted from outside; and an output unit operable to output a result of arithmetic-logic operation performed by the arithmetic-logic unit; wherein the memory unit, the arithmetic-logic unit, and the output unit are included in a functional block, and an output line of each of the memory unit is connected only to one of at least one of the arithmetic-logic unit.
摘要翻译：本发明的半导体器件包括：用于存储数据的非易失性存储单元中的至少一个; 算术逻辑单元中的至少一个，其可操作以使用存储在存储单元中的数据和从外部输入的数据执行算术运算; 以及输出单元，其可操作以输出由所述算术单元执行的算术逻辑运算的结果; 其中所述存储器单元，所述算术逻辑单元和所述输出单元包括在功能块中，并且所述存储器单元中的每一个的输出线仅与所述算术单元中的至少一个连接。

4. 发明申请

US20070063238A1 Semiconductor memory and driving method for the same 失效
标题翻译：半导体存储器和驱动方法相同
公开(公告)号：US20070063238A1
公开(公告)日：2007-03-22
申请号：US11520011
申请日：2006-09-13
申请人： Kazuhiro Kaibara , Shinzo Koyama , Yoshihisa Kato
发明人： Kazuhiro Kaibara , Shinzo Koyama , Yoshihisa Kato
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L21/28291 , H01L29/78391
摘要： A semiconductor memory includes a conducting film formed on a substrate; a ferroelectric film formed above or below the conducting film; a source electrode and a drain electrode disposed in positions opposing the conducting film with the ferroelectric film sandwiched therebetween and spaced from each other; and an insulating film formed between the source electrode and the drain electrode.
摘要翻译：半导体存储器包括形成在基板上的导电膜; 形成在导电膜上方或下方的铁电膜; 源电极和漏电极，设置在与导电膜相对的位置，铁电体膜夹在它们之间并彼此间隔开; 以及形成在源电极和漏电极之间的绝缘膜。

5. 发明申请

US20050117394A1 Switch matrix circuit, logical operation circuit, and switch circuit 有权
标题翻译：开关矩阵电路，逻辑运算电路和开关电路
公开(公告)号：US20050117394A1
公开(公告)日：2005-06-02
申请号：US11023831
申请日：2004-12-28
申请人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
IPC分类号： G11C11/22 , H03K17/24 , H03K17/693 , H03K19/177 , H04Q3/52 , G11C11/34
CPC分类号： H03K17/693 , G11C11/22 , H01L2924/0002 , H03K17/24 , H03K19/17712 , H01L2924/00
摘要： A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.
摘要翻译：提供一种构造简单且能够可靠地控制开关电池的开关电路。由于开关单元SC中的晶体管M 1的栅极端子G 1仅连接到晶体管M 2的端子37，所以当晶体管M 2被设置为截止时，积聚在栅极的电荷的移动路径晶体管M 1的G 1被截止。因此，即使晶体管M 2被设置为导通状态并立即恢复为截止状态，晶体管M 1在对应于通过位线BL给出的开关数据的导通或截止状态下保持一段时间。可以使晶体管M 1在规定时间段内保持导通或截止状态，而不设置用于临时存储开关数据的特定电路。

6. 发明授权

US08227883B2 Solid-state imaging device and camera 有权
标题翻译：固态成像装置和相机
公开(公告)号：US08227883B2
公开(公告)日：2012-07-24
申请号：US12491472
申请日：2009-06-25
申请人： Masahiro Kasano , Shinzo Koyama
发明人： Masahiro Kasano , Shinzo Koyama
IPC分类号： H01L31/0232
CPC分类号： G02B5/201 , G02B5/282 , H01L27/14621
摘要： A solid-state imaging device having a color filter with high color reproducibility even in the case of using lighting of low color temperatures. The solid-state imaging device has a plurality of pixels arranged two-dimensionally, and comprises a color separation filter which allows transmission of light of a predetermined wavelength in incident light for each of the plurality of pixels, wherein the color separation filter includes: a visible-light and near-infrared filter having transmission bands in regions of a visible wavelength band and a near-infrared wavelength band; and a near-infrared normalization filter laminated with the visible-light and near-infrared filter, wherein the near-infrared normalization filter is substantially transparent in the visible wavelength band and a first near-infrared wavelength band, and is substantially not transparent in a second near-infrared wavelength band between the visible wavelength band and the first near-infrared wavelength band.
摘要翻译：即使在使用低色温的照明的情况下，也可以使用具有彩色再现性高的滤色片的固态成像装置。该固态成像装置具有二维排列的多个像素，并且包括允许在多个像素中的每一个的入射光中传输预定波长的光的分色滤光器，其中，所述分色滤光器包括：可见光和近红外滤光器，其在可见波长带和近红外波长带的区域中具有透射带; 以及层叠有可见光和近红外滤光器的近红外归一化滤光器，其中近红外归一化滤光器在可见波长带和第一近红外波长带中基本上是透明的，并且在第二近红外波长带在可见波长带和第一近红外波长带之间。

7. 发明授权

US08035710B2 Solid-state imaging device and signal processing method 有权
标题翻译：固态成像装置及信号处理方法
公开(公告)号：US08035710B2
公开(公告)日：2011-10-11
申请号：US12134261
申请日：2008-06-06
申请人： Shinzo Koyama
发明人： Shinzo Koyama
IPC分类号： H04N5/335 , H04N5/225 , H01L31/062 , H01L31/232
CPC分类号： G02B5/201 , G02B5/285 , H01L27/14621 , H01L27/14625 , H01L31/02165 , H04N5/332 , H04N9/045
摘要： A solid-state imaging device including a color filter having a filter characteristic more approaching to a human visual sensitivity is provided. The color filter including a group of dielectric layers has high-refractive-index-material films and low-refractive-index-material films, the high-refractive-index-material film and the low-refractive-index-material film being n films and (n−1) films, respectively, which are laminated alternately, n being an integer equal to or larger than 4. The color filter includes at least a red-transmission filter, a green-transmission filter, and a blue-transmission filter. The group of dielectric layers is common in the color filter and includes two of the high-refractive-index-material films and one of the low-refractive-index-material films positioned between and in contact with the two of high-refractive-index-material films. In the red-transmission filter, a first one of low-refractive-index-material films and a second one of low-refractive-index-material films, which are not in the group of dielectric layers, have a thickness different from each other.
摘要翻译：提供了一种包括具有更接近人类视觉灵敏度的滤波器特性的滤色器的固态成像装置。包括一组电介质层的滤色器具有高折射率材料膜和低折射率材料膜，高折射率材料膜和低折射率材料膜是n个膜和（n-1）膜，它们交替层叠，n是等于或大于4的整数。滤色器至少包括红色透射滤光片，绿色透射滤光片和蓝色透射滤光片。介电层组在彩色滤光片中是常见的，并且包括两个高折射率材料膜和位于两个高折射率材料膜之间的低折射率材料膜之一材料薄膜。在红色透射滤光片中，不在介电层组中的低折射率材料薄膜和低折射率材料薄膜中的第一种具有彼此不同的厚度。

8. 发明授权

US07218142B2 Switch matrix circuit, logical operation circuit, and switch circuit 有权
标题翻译：开关矩阵电路，逻辑运算电路和开关电路
公开(公告)号：US07218142B2
公开(公告)日：2007-05-15
申请号：US11023831
申请日：2004-12-28
申请人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K17/693 , G11C11/22 , H01L2924/0002 , H03K17/24 , H03K19/17712 , H01L2924/00
摘要： A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.
摘要翻译：提供一种构造简单且能够可靠地控制开关电池的开关电路。由于开关单元SC中的晶体管M 1的栅极端子G 1仅连接到晶体管M 2的端子37，所以当晶体管M 2被设置为截止时，积聚在栅极的电荷的移动路径关断晶体管M 1的G 1。因此，即使晶体管M 2被设置为导通状态并立即恢复为截止状态，晶体管M 1在对应于通过位线BL给出的开关数据的导通或截止状态下保持一段时间。可以使晶体管M 1在规定时间段内保持导通或截止状态，而不设置用于临时存储开关数据的特定电路。

9. 发明授权

US07629635B2 Semiconductor memory and driving method for the same 失效
标题翻译：半导体存储器和驱动方法相同
公开(公告)号：US07629635B2
公开(公告)日：2009-12-08
申请号：US11520011
申请日：2006-09-13
申请人： Kazuhiro Kaibara , Shinzo Koyama , Yoshihisa Kato
发明人： Kazuhiro Kaibara , Shinzo Koyama , Yoshihisa Kato
IPC分类号： H01L29/51
CPC分类号： H01L27/11502 , H01L21/28291 , H01L29/78391
摘要： A semiconductor memory includes a conducting film formed on a substrate; a ferroelectric film formed above or below the conducting film; a source electrode and a drain electrode disposed in positions opposing the conducting film with the ferroelectric film sandwiched therebetween and spaced from each other; and an insulating film formed between the source electrode and the drain electrode.
摘要翻译：半导体存储器包括形成在基板上的导电膜; 形成在导电膜上方或下方的铁电膜; 源电极和漏电极，设置在与导电膜相对的位置，铁电体膜夹在它们之间并彼此间隔开; 以及形成在源电极和漏电极之间的绝缘膜。

10. 发明授权

US07039847B2 Coding-decoding device and method for conversion of binary sequences 失效
标题翻译：用于转换二进制序列的编码解码装置和方法
公开(公告)号：US07039847B2
公开(公告)日：2006-05-02
申请号：US10238984
申请日：2002-09-09
申请人： Hiroshi Nozawa , Shinzo Koyama , Masao Takayama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Masao Takayama , Yoshikazu Fujimori
IPC分类号： G11C29/00
CPC分类号： G11C7/1006
摘要： A coding-decoding device and a coding-decoding method that take less time for coding and decoding are provided while using less number of logic gates. A memory device 15 substantially stores b pieces of conversion logic equations produced with a conversion logic equation producing device 13. An operation device 17 has a programmable hardware logic circuit to constitute logics sequentially according to plural execution unit logic equations obtained by dividing b pieces of conversion logic equations stored in the memory device 15 into execution units for respective execution unit logic equations using the hardware logic circuit. Besides, the operation device 17 sequentially divides and calculates the second sentences from the first sentences according to the constituted logics. An output device 19 collects and outputs the second sentences calculated with the operation device 17.
摘要翻译：在使用较少数量的逻辑门的同时，提供了编码解码装置和编码解码方法，其中编码解码时间较短。存储器装置15基本上存储由转换逻辑方程产生装置13产生的b个转换逻辑方程式。操作装置17具有可编程硬件逻辑电路，以根据通过使用硬件逻辑电路将存储在存储器件15中的b个转换逻辑方程分成执行单元逻辑方程而获得的多个执行单元逻辑方程来顺序地构成逻辑。此外，操作装置17根据构成的逻辑顺序地分割和计算来自第一句子的第二句子。输出装置19收集并输出用操作装置17计算的第二句子。

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