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1. 发明授权

US07218142B2 Switch matrix circuit, logical operation circuit, and switch circuit 有权
标题翻译：开关矩阵电路，逻辑运算电路和开关电路
公开(公告)号：US07218142B2
公开(公告)日：2007-05-15
申请号：US11023831
申请日：2004-12-28
申请人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K17/693 , G11C11/22 , H01L2924/0002 , H03K17/24 , H03K19/17712 , H01L2924/00
摘要： A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.
摘要翻译：提供一种构造简单且能够可靠地控制开关电池的开关电路。由于开关单元SC中的晶体管M 1的栅极端子G 1仅连接到晶体管M 2的端子37，所以当晶体管M 2被设置为截止时，积聚在栅极的电荷的移动路径关断晶体管M 1的G 1。因此，即使晶体管M 2被设置为导通状态并立即恢复为截止状态，晶体管M 1在对应于通过位线BL给出的开关数据的导通或截止状态下保持一段时间。可以使晶体管M 1在规定时间段内保持导通或截止状态，而不设置用于临时存储开关数据的特定电路。

2. 发明授权

US07039847B2 Coding-decoding device and method for conversion of binary sequences 失效
标题翻译：用于转换二进制序列的编码解码装置和方法
公开(公告)号：US07039847B2
公开(公告)日：2006-05-02
申请号：US10238984
申请日：2002-09-09
申请人： Hiroshi Nozawa , Shinzo Koyama , Masao Takayama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Masao Takayama , Yoshikazu Fujimori
IPC分类号： G11C29/00
CPC分类号： G11C7/1006
摘要： A coding-decoding device and a coding-decoding method that take less time for coding and decoding are provided while using less number of logic gates. A memory device 15 substantially stores b pieces of conversion logic equations produced with a conversion logic equation producing device 13. An operation device 17 has a programmable hardware logic circuit to constitute logics sequentially according to plural execution unit logic equations obtained by dividing b pieces of conversion logic equations stored in the memory device 15 into execution units for respective execution unit logic equations using the hardware logic circuit. Besides, the operation device 17 sequentially divides and calculates the second sentences from the first sentences according to the constituted logics. An output device 19 collects and outputs the second sentences calculated with the operation device 17.
摘要翻译：在使用较少数量的逻辑门的同时，提供了编码解码装置和编码解码方法，其中编码解码时间较短。存储器装置15基本上存储由转换逻辑方程产生装置13产生的b个转换逻辑方程式。操作装置17具有可编程硬件逻辑电路，以根据通过使用硬件逻辑电路将存储在存储器件15中的b个转换逻辑方程分成执行单元逻辑方程而获得的多个执行单元逻辑方程来顺序地构成逻辑。此外，操作装置17根据构成的逻辑顺序地分割和计算来自第一句子的第二句子。输出装置19收集并输出用操作装置17计算的第二句子。

3. 发明授权

US06903572B2 Switch matrix circuit, logical operation circuit, and switch circuit 有权
标题翻译：开关矩阵电路，逻辑运算电路和开关电路
公开(公告)号：US06903572B2
公开(公告)日：2005-06-07
申请号：US10238037
申请日：2002-09-09
申请人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
IPC分类号： G11C11/22 , H03K17/24 , H03K17/693 , H03K19/177 , H04Q3/52
CPC分类号： H03K17/693 , G11C11/22 , H01L2924/0002 , H03K17/24 , H03K19/17712 , H01L2924/00
摘要： A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.
摘要翻译：提供一种构造简单且能够可靠地控制开关电池的开关电路。由于开关单元SC中的晶体管M 1的栅极端子G 1仅连接到晶体管M 2的端子37，所以当晶体管M 2被设置为截止时，在栅极G处累积的电荷的移动路径晶体管M 1的1被截止。因此，即使晶体管M 2被设置为导通状态并立即恢复为截止状态，晶体管M 1在对应于通过位线BL给出的开关数据的导通或截止状态下保持一段时间。可以使晶体管M 1在规定时间段内保持导通或截止状态，而不设置用于临时存储开关数据的特定电路。

4. 发明申请

US20050117394A1 Switch matrix circuit, logical operation circuit, and switch circuit 有权
标题翻译：开关矩阵电路，逻辑运算电路和开关电路
公开(公告)号：US20050117394A1
公开(公告)日：2005-06-02
申请号：US11023831
申请日：2004-12-28
申请人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Yoshikazu Fujimori
IPC分类号： G11C11/22 , H03K17/24 , H03K17/693 , H03K19/177 , H04Q3/52 , G11C11/34
CPC分类号： H03K17/693 , G11C11/22 , H01L2924/0002 , H03K17/24 , H03K19/17712 , H01L2924/00
摘要： A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.
摘要翻译：提供一种构造简单且能够可靠地控制开关电池的开关电路。由于开关单元SC中的晶体管M 1的栅极端子G 1仅连接到晶体管M 2的端子37，所以当晶体管M 2被设置为截止时，积聚在栅极的电荷的移动路径晶体管M 1的G 1被截止。因此，即使晶体管M 2被设置为导通状态并立即恢复为截止状态，晶体管M 1在对应于通过位线BL给出的开关数据的导通或截止状态下保持一段时间。可以使晶体管M 1在规定时间段内保持导通或截止状态，而不设置用于临时存储开关数据的特定电路。

5. 发明授权

US07038930B2 Memory device with function to perform operation, and method of performing operation and storage 失效
标题翻译：具有执行功能的存储器件，以及执行操作和存储的方法
公开(公告)号：US07038930B2
公开(公告)日：2006-05-02
申请号：US10844069
申请日：2004-05-12
申请人： Hiroshi Nozawa , Hiroaki Kato , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Hiroaki Kato , Yoshikazu Fujimori
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： To provide a memory device with a function to perform an operation and a method of performing an operation and storage which can save space and cost and which can start, immediately after the power source is recovered, the processing which was being performed at the time of power failure. A memory cell MC can store two independent data sets; DRAM data (volatile data) and FeRAM data (non-volatile data). Thus, the number of memory cells can be reduced to a half. Also, the DRAM data to be used in the next operation of the two data sets which have been read out for the previous operation are temporarily held in a hold circuit 21 of an operation unit OU and then written back into the memory cell MC in a non-volatile manner as new FeRAM data for preparation of the next operation. Thus, even when the power source is shut down by an unexpected trouble, the data necessary for the next operation are not lost.
摘要翻译：为了提供具有执行操作的功能的存储器件和执行操作和存储的方法，其可以节省空间和成本，并且可以在电源恢复之后立即开始执行正在执行的处理电源（检测）失败。存储单元MC可以存储两个独立的数据集; DRAM数据（易失性数据）和FeRAM数据（非易失性数据）。因此，存储器单元的数量可以减少到一半。此外，将用于在先前操作中读出的两个数据组的下次操作中使用的DRAM数据被暂时保存在操作单元OU的保持电路21中，然后被写回到存储单元MC中作为新的FeRAM数据的非易失性方式，用于准备下一个操作。因此，即使当电源被意外的故障关闭时，下一个操作所需的数据也不会丢失。

6. 发明授权

US07317794B2 Enciphering and deciphering apparatus, and enciphering and deciphering method 失效
标题翻译：加密和解密装置，以及加密和解密方法
公开(公告)号：US07317794B2
公开(公告)日：2008-01-08
申请号：US10378982
申请日：2003-03-03
申请人： Hiroshi Nozawa , Masao Takayama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Masao Takayama , Yoshikazu Fujimori
IPC分类号： H04L9/28
CPC分类号： H04L9/302 , H04L2209/12
摘要： The present invention aims at providing a novel enciphering and deciphering apparatus and an enciphering and deciphering method related thereto, which are respectively capable of contracting the time required for enciphering and deciphering processes and decreasing the number of logic gates provided in the apparatus. Essentially based on an equation Xki=1+Σ((J=1, i)iCj·Xk−1j) and also based on an initial value consisting of a group of power raising values Xk0j corresponding to j=1 through m in relation to k−1=k0, an arithmetic operating unit 21 seeks a second expression Yk1 by serially computing a group of power raising values Xki corresponding to i=1 through m in relation to one unit of k shown in the above equation in a range from k=k0+1 up to k=k1 by applying binomial coefficients stored in a coefficient memory unit 17. Accordingly, once those binomial coefficients corresponding to predetermined integers n and m are stored in memory, thenceforth, it is possible to contract the time required for executing an enciphering or deciphering process related to identical integers n and m.
摘要翻译：本发明旨在提供一种新颖的加密和解密装置及其相关的加密和解密方法，它们能够缩短加密和解密处理所需的时间并减少设备中提供的逻辑门数。基本上基于方程式X 1 i S iΣΣ（（J = 1，i）＆lt; i＆lt; 并且还基于由一组增力值组成的初始值X＆lt; k＆gt;＆lt; j＆gt;＆lt; j＆gt; 相对于k-1 = k0对应于j = 1到m的算术运算单元21通过串联计算一组功率提升值X 存储在系数存储单元17中的系数。因此，一旦对应于预定的整数n和m的二项式系数被存储在存储器中，则可以缩小执行与相同的整数n和m相关的加密或解密处理所需的时间。

7. 发明授权

US09100014B2 Nonvolatile storage gate, operation method for the same, and nonvolatile storage gate embedded logic circuit, and operation method for the same 有权
标题翻译：非易失性存储门，其操作方法和非易失性存储门嵌入式逻辑电路及其操作方法
公开(公告)号：US09100014B2
公开(公告)日：2015-08-04
申请号：US12919336
申请日：2009-01-08
申请人： Hiromitsu Kimura , Takaaki Fuchikami , Yoshikazu Fujimori
发明人： Hiromitsu Kimura , Takaaki Fuchikami , Yoshikazu Fujimori
IPC分类号： G06F12/00 , H03K19/20 , G11C11/22 , H03K3/037
CPC分类号： H03K19/20 , G11C11/22 , H03K3/0375
摘要： Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal.
摘要翻译：提供了嵌入非易失性存储栅极的非易失性存储栅极嵌入式逻辑电路，其可以在电源切断之后保持数据，并且可以在同时切换到待机状态的同时切断电源。非易失性存储门嵌入逻辑电路包括具有逻辑门的逻辑计算单元和具有非易失性存储元件的非易失性存储栅极，与非易失性存储元件邻接配置的数据接口控制单元，以及接收非易失性存储器用于从非易失性存储元件读出的数据的控制信号和非易失性存储元件的数据写入;以及与非易失性存储元件邻接设置的易失性存储元件，接收数据输入信号和时钟信号，并输出数据输出信号。

8. 发明申请

US20100321975A1 FERROELECTRIC MEMORY DEVICE 有权
标题翻译：电磁存储器件
公开(公告)号：US20100321975A1
公开(公告)日：2010-12-23
申请号：US12918396
申请日：2009-01-08
申请人： Hiromitsu Kimura , Takaaki Fuchikami , Yoshikazu Fujimori
发明人： Hiromitsu Kimura , Takaaki Fuchikami , Yoshikazu Fujimori
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22 , G11C7/12 , G11C11/4094
摘要： By separately setting a capacitor on BL depending on whether the mode is a DRAM mode or an FRAM mode, it is compatible with improvement in a speed by BL capacitor reduction in the DRAM mode and a sufficient BL capacitance in the FRAM mode.A ferroelectric memory device includes: a plurality of bit lines BL disposed in a column direction; a plurality of word lines WL disposed in a row direction; a plurality of plate lines PL and a bit line capacitor control signal BLC; a ferroelectric memory cell (32) disposed at an intersection of the plurality of bit lines BL, the plurality of word lines WL, and the plurality of plate lines PL, and composed of a ferroelectric capacitor CF and a memory cell transistor QM; and a load capacitor adjustment cell (34) disposed at an intersection of the plurality of bit lines BL and the bit line capacitor control signal BLC, and composed of a load capacitor CL and a load capacitor adjustment transistor QL.
摘要翻译：通过根据模式是DRAM模式还是FRAM模式单独设置BL上的电容器，通过DRAM模式下的BL电容降低和FRAM模式下的足够的BL电容来提高速度。铁电存储器件包括：沿列方向设置的多个位线BL; 沿行方向布置的多个字线WL; 多个板线PL和位线电容器控制信号BLC; 设置在所述多个位线BL，所述多个字线WL和所述多个板极线PL的交点的铁电存储器单元（32），并且由铁电电容器CF和存储单元晶体管QM构成; 以及设置在多个位线BL和位线电容器控制信号BLC的交点处的负载电容器调整单元（34），由负载电容器CL和负载电容调整用晶体管QL构成。

9. 发明申请

US20100245970A1 LIGHT CONTROL DEVICE, SEMICONDUCTOR WAFER, AND LIGHT CONTROL SYSTEM 有权
标题翻译：灯控制装置，半导体波束和灯控制系统
公开(公告)号：US20100245970A1
公开(公告)日：2010-09-30
申请号：US12743929
申请日：2008-11-20
申请人： Yoshikazu Fujimori , Tsuyoshi Fujii
发明人： Yoshikazu Fujimori , Tsuyoshi Fujii
IPC分类号： G02F1/03 , H01L29/04
CPC分类号： G02F1/05 , G02F1/0136 , G02F2201/124
摘要： A light control device includes: a single crystal substrate (10); an electro-optic thin film (20) which is provided on the single crystal substrate (10) and has an electro-optic effect; and a plurality of electrodes (30, 40) which are provided along a crystal axis of the electro-optic thin film and apply an electrical field along the crystal axis of the electro-optic thin film (20).
摘要翻译：光控制装置包括：单晶基板（10）; 设置在单晶基板（10）上并具有电光效应的电光薄膜（20）以及沿着电光薄膜的晶轴设置并沿着电光薄膜（20）的晶轴施加电场的多个电极（30,40）。

10. 发明授权

US07672034B2 Method for manufacturing optical modulator, optical modulator, and optical modulation system 有权
标题翻译：光调制器，光调制器和光调制系统的制造方法
公开(公告)号：US07672034B2
公开(公告)日：2010-03-02
申请号：US11911314
申请日：2006-04-07
申请人： Yoshikazu Fujimori
发明人： Yoshikazu Fujimori
IPC分类号： G02F1/03
CPC分类号： G02F1/03 , B82Y20/00 , G02F1/017 , G02F1/055 , G02F1/21 , G02F2001/213
摘要： A manufacturing method is provided for a light modulation device that improves utilization efficiency of light. After forming a first reflective layer using a metallic material such as Pt or the like, on a substrate, a light modulating film is formed using an electro-optic material in which refractive index changes in accordance with an applied electrical field. After that, planarization is carried out so that irregularities on an upper surface of the light modulating film are less than or equal to 1/100 of the wavelength of light incident on the light modulation device. A transparent electrode is then formed using ITO, ZnO, or the like, on the light modulating film, and a second reflective layer including a dielectric multilayer is formed.
摘要翻译：提供了提高光的利用效率的光调制装置的制造方法。在使用诸如Pt等的金属材料形成第一反射层之后，在基板上，使用其中折射率根据所施加的电场而改变的电光材料形成光调制膜。之后，进行平坦化，使得光调制膜的上表面上的凹凸小于或等于入射在光调制装置上的光的波长的1/100。然后在光调制膜上使用ITO，ZnO等形成透明电极，形成包括电介质多层的第二反射层。

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