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1. 发明授权

US07039847B2 Coding-decoding device and method for conversion of binary sequences 失效
标题翻译：用于转换二进制序列的编码解码装置和方法
公开(公告)号：US07039847B2
公开(公告)日：2006-05-02
申请号：US10238984
申请日：2002-09-09
申请人： Hiroshi Nozawa , Shinzo Koyama , Masao Takayama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Shinzo Koyama , Masao Takayama , Yoshikazu Fujimori
IPC分类号： G11C29/00
CPC分类号： G11C7/1006
摘要： A coding-decoding device and a coding-decoding method that take less time for coding and decoding are provided while using less number of logic gates. A memory device 15 substantially stores b pieces of conversion logic equations produced with a conversion logic equation producing device 13. An operation device 17 has a programmable hardware logic circuit to constitute logics sequentially according to plural execution unit logic equations obtained by dividing b pieces of conversion logic equations stored in the memory device 15 into execution units for respective execution unit logic equations using the hardware logic circuit. Besides, the operation device 17 sequentially divides and calculates the second sentences from the first sentences according to the constituted logics. An output device 19 collects and outputs the second sentences calculated with the operation device 17.
摘要翻译：在使用较少数量的逻辑门的同时，提供了编码解码装置和编码解码方法，其中编码解码时间较短。存储器装置15基本上存储由转换逻辑方程产生装置13产生的b个转换逻辑方程式。操作装置17具有可编程硬件逻辑电路，以根据通过使用硬件逻辑电路将存储在存储器件15中的b个转换逻辑方程分成执行单元逻辑方程而获得的多个执行单元逻辑方程来顺序地构成逻辑。此外，操作装置17根据构成的逻辑顺序地分割和计算来自第一句子的第二句子。输出装置19收集并输出用操作装置17计算的第二句子。

2. 发明授权

US07317794B2 Enciphering and deciphering apparatus, and enciphering and deciphering method 失效
标题翻译：加密和解密装置，以及加密和解密方法
公开(公告)号：US07317794B2
公开(公告)日：2008-01-08
申请号：US10378982
申请日：2003-03-03
申请人： Hiroshi Nozawa , Masao Takayama , Yoshikazu Fujimori
发明人： Hiroshi Nozawa , Masao Takayama , Yoshikazu Fujimori
IPC分类号： H04L9/28
CPC分类号： H04L9/302 , H04L2209/12
摘要： The present invention aims at providing a novel enciphering and deciphering apparatus and an enciphering and deciphering method related thereto, which are respectively capable of contracting the time required for enciphering and deciphering processes and decreasing the number of logic gates provided in the apparatus. Essentially based on an equation Xki=1+Σ((J=1, i)iCj·Xk−1j) and also based on an initial value consisting of a group of power raising values Xk0j corresponding to j=1 through m in relation to k−1=k0, an arithmetic operating unit 21 seeks a second expression Yk1 by serially computing a group of power raising values Xki corresponding to i=1 through m in relation to one unit of k shown in the above equation in a range from k=k0+1 up to k=k1 by applying binomial coefficients stored in a coefficient memory unit 17. Accordingly, once those binomial coefficients corresponding to predetermined integers n and m are stored in memory, thenceforth, it is possible to contract the time required for executing an enciphering or deciphering process related to identical integers n and m.
摘要翻译：本发明旨在提供一种新颖的加密和解密装置及其相关的加密和解密方法，它们能够缩短加密和解密处理所需的时间并减少设备中提供的逻辑门数。基本上基于方程式X 1 i S iΣΣ（（J = 1，i）＆lt; i＆lt; 并且还基于由一组增力值组成的初始值X＆lt; k＆gt;＆lt; j＆gt;＆lt; j＆gt; 相对于k-1 = k0对应于j = 1到m的算术运算单元21通过串联计算一组功率提升值X 存储在系数存储单元17中的系数。因此，一旦对应于预定的整数n和m的二项式系数被存储在存储器中，则可以缩小执行与相同的整数n和m相关的加密或解密处理所需的时间。

3. 发明授权

US08466820B2 Oversampling A/D converter 有权
公开(公告)号：US08466820B2
公开(公告)日：2013-06-18
申请号：US13025666
申请日：2011-02-11
申请人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
发明人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
IPC分类号： H03M3/00
CPC分类号： H03M1/12 , H03M3/344 , H03M3/43 , H03M3/454
摘要： An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

4. 发明申请

US20120293346A1 OFFSET CORRECTION DEVICE OF COMPARATOR 有权
标题翻译：比较器偏移校正装置
公开(公告)号：US20120293346A1
公开(公告)日：2012-11-22
申请号：US13564496
申请日：2012-08-01
申请人： Masao Takayama , Kazuo Matsukawa
发明人： Masao Takayama , Kazuo Matsukawa
IPC分类号： H03L5/00 , H03M3/02 , H03M1/12
CPC分类号： H03M1/1023 , H03K3/356139 , H03K5/2481 , H03K5/249 , H03M1/36
摘要： A comparator offset correction device opens an open switch 205 and closes a short-circuit switch 204 in offset correction of a comparator 201. In this state, a controller 203 allows the comparator 201 to repeat, more than once, the operation of comparing reference voltages 101 input to two input terminals with each other. The filter 202 outputs a frequency signal obtained by smoothing a plurality of comparison results. Based on the frequency signal from the filter 202, the controller 203 outputs a threshold value control signal to the comparator 201 so that the ratio of a high-level voltage to a low-level voltage in the results of the comparison in the comparator 201 is 50%. Thus, even when a current which will be input may differ from a current which is currently input due to, for example, the influence of noise, the threshold value offset amount is normally corrected.
摘要翻译：比较器偏移校正装置打开开关205并在比较器201的偏移校正中闭合短路开关204.在该状态下，控制器203允许比较器201多次重复比较参考电压 101输入到两个输入端子。滤波器202输出通过平滑多个比较结果而获得的频率信号。基于来自滤波器202的频率信号，控制器203向比较器201输出阈值控制信号，使比较器201中的比较结果中的高电平电压与低电平电压的比率为 50％。因此，即使当输入的电流可能与由于例如噪声的影响而当前输入的电流不同时，通常校正阈值偏移量。

5. 发明授权

US08258990B2 Integrator, resonator, and oversampling A/D converter 有权
标题翻译：积分器，谐振器和过采样A / D转换器
公开(公告)号：US08258990B2
公开(公告)日：2012-09-04
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
IPC分类号： H03M3/00
CPC分类号： H03M3/454 , H03M3/404 , H03M3/43
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译：积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。

6. 发明授权

US07638459B2 Layered composition and processes for preparing and using the composition 有权
标题翻译：用于制备和使用组合物的分层组合物和方法
公开(公告)号：US07638459B2
公开(公告)日：2009-12-29
申请号：US11137189
申请日：2005-05-25
申请人： Dean E. Rende , James E. Rekoske , Jeffery C. Bricker , Jeffrey L. Boike , Masao Takayama , Kouji Hara , Nobuyuki Aoi
发明人： Dean E. Rende , James E. Rekoske , Jeffery C. Bricker , Jeffrey L. Boike , Masao Takayama , Kouji Hara , Nobuyuki Aoi
IPC分类号： B01J23/00 , B01J21/00 , B01J29/00 , B01J20/00
CPC分类号： C07C5/321 , B01J21/063 , B01J21/066 , B01J23/38 , B01J32/00 , B01J37/0036 , B01J37/0045 , B01J37/0219 , B01J37/0221 , C07C5/333 , C10G11/04 , C10G45/40 , C10G45/62 , C10G47/14 , C07C15/46
摘要： A layered composition which can be used in various processes has been developed. The composition comprises an inner core such as a cordierite core and an outer layer comprising a refractory inorganic oxide, a fibrous component and an inorganic binder. The refractory inorganic oxide layer can be alumina, zirconia, titania, etc. while the fibrous component can be titania fibers, silica fibers, carbon fibers, etc. The inorganic oxide binder can be alumina, silica, zirconia, etc. The layer can also contain catalytic metals such as gold and platinum plus other modifiers. The layered composition is prepared by coating the inner core with a slurry comprising the refractory inorganic oxide, fibrous component, an inorganic binder precursor and an organic binding agent such as polyvinyl alcohol. The composition can be used in various hydrocarbon conversion processes.
摘要翻译：已经开发了可用于各种方法的分层组合物。该组合物包括内核，例如堇青石芯，外层包含耐火无机氧化物，纤维组分和无机粘合剂。难熔无机氧化物层可以是氧化铝，氧化锆，二氧化钛等，而纤维成分可以是二氧化钛纤维，二氧化硅纤维，碳纤维等。无机氧化物粘合剂可以是氧化铝，二氧化硅，氧化锆等。该层也可以含有催化金属如金和铂加其他改性剂。通过用包含耐火无机氧化物，纤维组分，无机粘合剂前体和有机粘合剂如聚乙烯醇的浆料涂覆内芯来制备层状组合物。该组合物可用于各种烃转化方法中。

7. 发明申请

US20080287703A1 LAYERED COMPOSITION AND PROCESSES FOR PREPARING AND USING THE COMPOSITION 有权
标题翻译：层状组合物和制备和使用组合物的方法
公开(公告)号：US20080287703A1
公开(公告)日：2008-11-20
申请号：US12098951
申请日：2008-04-07
申请人： Tao Wang , Dean E. Rende , James E. Rekoske , Jeffery C. Bricker , Jeffrey L. Boike , Masao Takayama , Kouji Hara , Nobuyuki Aoi
发明人： Tao Wang , Dean E. Rende , James E. Rekoske , Jeffery C. Bricker , Jeffrey L. Boike , Masao Takayama , Kouji Hara , Nobuyuki Aoi
IPC分类号： C07C67/055
CPC分类号： B01J37/0242 , B01J23/44 , B01J23/52 , B01J23/58 , B01J37/0219 , B01J37/0221 , C07C67/055 , C07C69/01 , C07C69/15
摘要： A layered composition which can be used in various processes has been developed. The composition comprises an inner core such as a cordierite core and an outer layer comprising a refractory inorganic oxide, a fibrous component and an inorganic binder. The refractory inorganic oxide layer can be alumina, zirconia, titania, etc. while the fibrous component can be titania fibers, silica fibers, carbon fibers, etc. The inorganic oxide binder can be alumina, silica, zirconia, etc. The layer can also contain catalytic metals such as gold and platinum plus other modifiers. The layered composition is prepared by coating the inner core with a slurry comprising the refractory inorganic oxide, fibrous component, an inorganic binder precursor and an organic binding agent such as polyvinyl alcohol. The composition can be used in various hydrocarbon conversion processes including production of vinyl acetate.
摘要翻译：已经开发了可用于各种方法的分层组合物。该组合物包括内核，例如堇青石芯，外层包含耐火无机氧化物，纤维组分和无机粘合剂。难熔无机氧化物层可以是氧化铝，氧化锆，二氧化钛等，而纤维成分可以是二氧化钛纤维，二氧化硅纤维，碳纤维等。无机氧化物粘合剂可以是氧化铝，二氧化硅，氧化锆等。该层也可以含有催化金属如金和铂加其他改性剂。通过用包含耐火无机氧化物，纤维组分，无机粘合剂前体和有机粘合剂如聚乙烯醇的浆料涂覆内芯来制备层状组合物。该组合物可用于各种烃转化方法，包括生产乙酸乙烯酯。

8. 发明授权

US06177381B1 Layered catalyst composition and processes for preparing and using the composition 有权
公开(公告)号：US06177381B1
公开(公告)日：2001-01-23
申请号：US09185189
申请日：1998-11-03
申请人： Robert H Jensen , Jeffrey C. Bricker , Qianjun Chen , Masaru Tatsushima , Kenji Kikuchi , Masao Takayama , Koji Hara , Isao Tsunokuma , Hiroyuki Serizawa
发明人： Robert H Jensen , Jeffrey C. Bricker , Qianjun Chen , Masaru Tatsushima , Kenji Kikuchi , Masao Takayama , Koji Hara , Isao Tsunokuma , Hiroyuki Serizawa
IPC分类号： B01J2300
CPC分类号： B01J23/626 , B01J23/40 , B01J29/06 , B01J29/7007 , B01J37/0219 , B01J37/0242 , B01J37/0246 , Y10T428/2991 , Y10T428/2993
摘要： This invention relates to a layered catalyst composition, a process for preparing the composition and processes for using the composition. The catalyst composition comprises an inner core such as alpha-alumina, and an outer layer bonded to the inner core composed of an outer refractory inorganic oxide such as gamma-alumina. The outer layer has uniformly dispersed thereon a platinum group metal such as platinum and a promoter metal such as tin. The composition also contains a modifier metal such as lithium. The catalyst composition shows improved durability and selectivity for dehydrogenating hydrocarbons.

9. 发明授权

US08823567B2 Resonator, delta-sigma modulator, and wireless communication device 有权
标题翻译：谐振器，Δ-Σ调制器和无线通信设备
公开(公告)号：US08823567B2
公开(公告)日：2014-09-02
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
IPC分类号： H03M3/00 , H03H11/04
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译：两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件连接在每个中间节点和信号输入端子之间。并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。

10. 发明申请

US20110200077A1 DELTA-SIGMA MODULATOR AND WIRELESS COMMUNICATION DEVICE 审中-公开
标题翻译： DELTA-SIGMA调制器和无线通信设备
公开(公告)号：US20110200077A1
公开(公告)日：2011-08-18
申请号：US13094519
申请日：2011-04-26
申请人： Yosuke MITANI , Kazuo Matsukawa , Masao Takayama , Shiro Dosho
发明人： Yosuke MITANI , Kazuo Matsukawa , Masao Takayama , Shiro Dosho
IPC分类号： H04B1/38 , H03M3/02
CPC分类号： H03M3/388 , H03M3/424 , H03M3/456
摘要： In a DSM including a loop in which an output signal of a quantizer is digitally processed, and fed back through a DAC to an analog filter, the quantizer quantizes an analog signal from an analog filter section to output a digital signal. The digital signal from the quantizer is digitally processed in a first-order recursive filter circuit including a variable gain amplifier and a delay element. A LUT receives both the digital signal from the quantizer and a table control signal, which is an output signal from the recursive filter circuit, and stores in advance compensation values corresponding to the both signals. A compensation value from the LUT is used to provide a digital output signal compensated for a delay. The digital output signal is converted into an analog signal in the DAC, and then subtracted from an analog input signal in the analog filter section.
摘要翻译：在包括量化器的输出信号被数字处理并通过DAC反馈到模拟滤波器的环路的DSM中，量化器对来自模拟滤波器部分的模拟信号进行量化以输出数字信号。来自量化器的数字信号在包括可变增益放大器和延迟元件的一阶递归滤波器电路中进行数字处理。 LUT接收来自量化器的数字信号和作为来自递归滤波器电路的输出信号的表控制信号，并且预先存储对应于两个信号的补偿值。来自LUT的补偿值用于提供补偿延迟的数字输出信号。数字输出信号在DAC中转换为模拟信号，然后从模拟滤波器部分的模拟输入信号中减去。

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