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1. 发明授权

US07960253B2 Thin silicon wafer with high gettering ability and production method thereof 有权
标题翻译：具有高吸气能力的薄硅晶片及其制造方法
公开(公告)号：US07960253B2
公开(公告)日：2011-06-14
申请号：US12436692
申请日：2009-05-06
申请人： Takaaki Shiota , Takashi Nakayama , Tomoyuki Kabasawa
发明人： Takaaki Shiota , Takashi Nakayama , Tomoyuki Kabasawa
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/3225 , H01L21/02024
摘要： In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 μm and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.
摘要翻译：在具有氧沉淀层的硅晶片中，从晶片表面到氧沉淀层的DZ层的深度为2〜10μm，氧沉淀层的氧析出物浓度为5×10 7个/ cm 3 / cm 3以上。

2. 发明申请

US20090278239A1 Silicon Wafer and Production Method Thereof 有权
标题翻译：硅晶片及其制作方法
公开(公告)号：US20090278239A1
公开(公告)日：2009-11-12
申请号：US12436692
申请日：2009-05-06
申请人： Takaaki Shiota , Takashi Nakayama , Tomoyuki Kabasawa
发明人： Takaaki Shiota , Takashi Nakayama , Tomoyuki Kabasawa
IPC分类号： H01L29/36 , H01L21/322
CPC分类号： H01L21/3225 , H01L21/02024
摘要： In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 μm and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.
摘要翻译：在具有氧沉淀层的硅晶片中，从晶片表面到氧气沉淀层的DZ层的深度为2〜10μm，氧沉淀层的氧析出物浓度为5×10 7个/ cm 3以上。

3. 发明申请

US20100009521A1 METHOD OF PRODUCING SEMICONDUCTOR WAFER 审中-公开
标题翻译：生产半导体波长的方法
公开(公告)号：US20100009521A1
公开(公告)日：2010-01-14
申请号：US12501331
申请日：2009-07-10
申请人： Takaaki Shiota , Wataru Itou , Takashi Nakayama
发明人： Takaaki Shiota , Wataru Itou , Takashi Nakayama
IPC分类号： H01L21/322
CPC分类号： H01L21/3225 , H01L21/02008 , Y02P80/30
摘要： There is provided a production method in which the beveling step conducted for preventing the cracking or chipping in a raw wafer during the grinding can be omitted when the raw wafer cut out from a crystalline ingot is processed into a double-side mirror-finished semiconductor wafer and a semiconductor wafer can be obtained cheaply by shortening the whole of the production steps for the semiconductor wafer and decreasing the machining allowance of silicon material in the semiconductor wafer to reduce the kerf loss of the semiconductor material as compared with the conventional method.The method is characterized by comprising a slicing step of cutting out a thin disc-shaped raw wafer from a crystalline ingot; a fixed grain bonded abrasive grinding step of sandwiching the raw wafer between a pair of upper and lower platens each having a pad of fixed grain bonded abrasive to simultaneously grind both surfaces of the raw wafer; a heat treating step of subjecting the raw wafer to a given heat treatment after the fixed grain bonded abrasive grinding step; and a one-side polishing step of polishing each of the both surfaces of the raw wafer after the heat treating step.
摘要翻译：提供了一种制造方法，其中当从晶体块切出的原始晶片被加工成双面镜面半导体晶片时，可以省略在研磨期间防止原始晶片中的开裂或碎裂所进行的斜切步骤通过缩短半导体晶片的整个生产步骤并减少半导体晶片中的硅材料的加工余量，可以廉价地获得半导体晶片，以减少半导体材料的切口损耗。该方法的特征在于包括从晶锭切割薄盘形原始晶片的切片步骤; 将原始晶片夹在一对上下压板之间的固定晶粒粘结磨料研磨步骤，每个上下压板均具有固定颗粒粘合磨料垫，以同时研磨原始晶片的两个表面; 热处理工序，在所述固定晶粒结合磨料研磨工序之后对所述原料晶片进行给定的热处理; 以及在热处理步骤之后对原始晶片的两个表面进行抛光的单面抛光步骤。

4. 发明授权

US07582540B2 Method for manufacturing SOI wafer 有权
标题翻译：制造SOI晶圆的方法
公开(公告)号：US07582540B2
公开(公告)日：2009-09-01
申请号：US11289307
申请日：2005-11-30
申请人： Takaaki Shiota , Yasuhiro Oura
发明人： Takaaki Shiota , Yasuhiro Oura
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L21/3226 , H01L21/76256
摘要： This method for manufacturing an SOI wafer includes: a step of forming insulating films in a front surface and a mirror-polished rear surface of an active layer wafer; a step of removing the insulating film in the front surface of the active layer wafer; a step of subjecting the active layer wafer to a rapid thermal annealing process; a step of bonding the active layer wafer and a support wafer with the insulating film formed in the rear surface therebetween so as to form a bonded wafer; a step of subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer; and a step of thinning the active layer wafer in the bonded wafer so as to form an SOI layer.
摘要翻译：制造SOI晶片的方法包括：在有源层晶片的前表面和镜面抛光的后表面中形成绝缘膜的步骤; 去除有源层晶片的前表面中的绝缘膜的步骤; 对活性层晶片进行快速热退火处理的步骤; 将有源层晶片和支撑晶片与其后表面中形成的绝缘膜接合以形成接合晶片的步骤; 使接合晶片进行用于粘结增强的热处理以提高有源层晶片和支撑晶片之间的结合强度的步骤; 以及使接合晶片中的有源层晶片变薄以形成SOI层的步骤。

5. 发明授权

US07122082B2 Silicon wafer and manufacturing method thereof 有权
标题翻译：硅晶片及其制造方法
公开(公告)号：US07122082B2
公开(公告)日：2006-10-17
申请号：US10706266
申请日：2003-11-13
申请人： Takaaki Shiota , Yoshinobu Nakada
发明人： Takaaki Shiota , Yoshinobu Nakada
IPC分类号： C30B15/14
CPC分类号： H01L21/3225 , C30B15/00 , C30B15/20 , C30B29/06 , H01L29/32
摘要： A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm−3 and 1×1011 cm−3.
摘要翻译：其中堆垛层错（SF）核分布在整个面内方向上的硅晶片，堆垛层错核的密度设定在0.5×10 8 cm -3以下的范围内， 3和1×10 11 cm -3 -3。

6. 发明授权

US07632349B2 Silicon wafer surface defect evaluation method 有权
标题翻译：硅晶片表面缺陷评估方法
公开(公告)号：US07632349B2
公开(公告)日：2009-12-15
申请号：US11467411
申请日：2006-08-25
申请人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
发明人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
IPC分类号： C30B33/00
CPC分类号： H01L22/12
摘要： There is provided a silicon wafer surface defect evaluation method capable of readily detecting a region where small crystal defects exist, the evaluation method comprising: a rapid heat treatment step of a silicon wafer from a silicon single-crystal ingot in an atmosphere which can nitride silicon at a temperature elevating speed of 10 to 150° C./second from a room temperature to temperatures between not lower than 1170° C. and less than a silicon melting point, holding the silicon wafer at the processing temperature for 1 to 120 seconds and then cooling the silicon wafer to the room temperature at a temperature lowering speed of 10 to 100° C./second; and a step of using a surface photo voltage method to calculate a minority carrier diffusion length on the wafer surface, thereby detecting a region on the wafer surface in which small COP's which cannot be detected at least by a particle counter exist.
摘要翻译：提供一种能够容易地检测出存在小晶体缺陷的区域的硅晶片表面缺陷评估方法，该评估方法包括：在能够将氮化硅的气氛中的硅单晶锭的硅晶片的快速热处理步骤以10〜150℃/秒的温度升温速度从室温升温至不低于1170℃，低于硅熔点，将硅晶片在处理温度下保持1〜120秒，然后以10〜100℃/秒的降温速度将硅晶片冷却至室温; 以及使用表面光电压法来计算晶片表面上的少数载流子扩散长度的步骤，从而检测晶片表面上至少存在无法检测到的小的COP的区域。

7. 发明申请

US20060121692A1 Method for manufacturing SOI wafer 有权
公开(公告)号：US20060121692A1
公开(公告)日：2006-06-08
申请号：US11289306
申请日：2005-11-30
申请人： Takaaki Shiota , Yasuhiro Oura
发明人： Takaaki Shiota , Yasuhiro Oura
IPC分类号： H01L21/46
CPC分类号： H01L21/76251
摘要： This method for manufacturing an SOI wafer includes: a step of subjecting a mirror-polished active layer wafer to a rapid thermal annealing treatment; a step of forming insulating films in a front surface and a rear surface of the active layer wafer; a step of bonding the active layer wafer and a support wafer with the insulating film therebetween so as to form a bonded wafer; a step of loading the bonded wafer on a wafer boat in a state such that a portion of the active layer wafer is in contact with the wafer boat, and then subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer in the bonded wafer; and a step of thinning a portion of the active layer wafer.

8. 发明授权

US06428619B1 Silicon wafer, and heat treatment method of the same and the heat-treated silicon wafer 有权
标题翻译：硅晶片及其热处理方法和热处理硅晶片
公开(公告)号：US06428619B1
公开(公告)日：2002-08-06
申请号：US09694163
申请日：2000-10-23
申请人： Hiroshi Koya , Hisashi Furuya , Yoji Suzuki , Yukio Muroi , Takaaki Shiota
发明人： Hiroshi Koya , Hisashi Furuya , Yoji Suzuki , Yukio Muroi , Takaaki Shiota
IPC分类号： C30B2502
CPC分类号： C30B29/06 , C30B33/00 , H01L21/3221 , H01L21/3225 , Y10T428/24942
摘要： A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment. Accordingly, the resulting silicon wafer with a polysilicon layer is of OSF fee and COP free, even when the wafer is subjected to the conventional OSF-manifesting heat treatment. The wafer with the polysilicon layer exerts a uniform gettering effect between the peripheral edge and center of the silicon wafer as a result of a uniform oxygen precipitation occurred at the entire surface of the silicon wafer.
摘要翻译：硅晶片的热处理方法具有以下步骤：制备氧浓度为1.2×1018原子/ cm3以下（旧ASTM）的硅晶片，不产生晶体起始粒子（COP'S）和间隙型大位错（L / D）; 通过在670℃±30℃的温度下的化学气相沉积在硅晶片的背面上形成厚度为0.1μm至1.6μm的多晶硅层。在氧气氛中，在1000℃±30℃下，将具有多晶硅层的硅晶片热处理2〜5小时，然后在1130℃±30℃下热处理1〜16小时。在该方法中，在其上形成多晶硅层之前的硅晶片是当晶片进行热处理时，氧化诱导堆垛层错（OSF）在晶片的中心处显现的晶片的类型。因此，即使当经过常规的OSF显示热处理时，所得到的具有多晶硅层的硅晶片也具有OSF费用和COP。具有多晶硅层的晶片在硅晶片的整个表面上发生均匀的氧沉淀的结果，在硅晶片的外围边缘和中心之间施加均匀的吸气效应。

9. 发明申请

US20070044709A1 Silicon Wafer Surface Defect Evaluation Method 有权
标题翻译：硅晶片表面缺陷评估方法
公开(公告)号：US20070044709A1
公开(公告)日：2007-03-01
申请号：US11467411
申请日：2006-08-25
申请人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
发明人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
IPC分类号： C30B15/00 , C30B21/06 , C30B27/02 , C30B28/10 , C30B30/04
CPC分类号： H01L22/12
摘要： There is provided a silicon wafer surface defect evaluation method capable of readily detecting a region where small crystal defects exist. A silicon wafer surface defect evaluation method according to the present invention is characterized by comprising: a rapid heat treatment step of applying a heat treatment to a silicon wafer cut out from a silicon single-crystal ingot in an atmosphere which can nitride silicon at a temperature elevating speed of 10 to 150° C./second from a room temperature to temperatures between not lower than 1170° C. and less than a silicon melting point, holding the silicon wafer at the processing temperature for 1 to 120 seconds and then cooling the silicon wafer to the room temperature at a temperature lowering speed of 10 to 100° C./second; and a step of using a surface photo voltage method to calculate a minority carrier diffusion length on the wafer surface, thereby detecting a region on the wafer surface in which small COP's which cannot be detected at least by a particle counter exist.
摘要翻译：提供了能够容易地检测存在小晶体缺陷的区域的硅晶片表面缺陷评估方法。根据本发明的硅晶片表面缺陷评估方法的特征在于包括：快速热处理步骤，在可以在温度为氮化硅的气氛中从硅单晶锭切出的硅晶片进行热处理将升温速度从室温升温至不低于1170℃至低于硅熔点的温度，将硅晶片在处理温度下保持1至120秒，然后冷却硅晶片以10〜100℃/秒的降温速度至室温; 以及使用表面光电压法来计算晶片表面上的少数载流子扩散长度的步骤，从而检测晶片表面上至少存在无法检测到的小的COP的区域。

10. 发明申请

US20060121696A1 Method for manufacturing SOI wafer 有权
公开(公告)号：US20060121696A1
公开(公告)日：2006-06-08
申请号：US11289307
申请日：2005-11-30
申请人： Takaaki Shiota , Yasuhiro Oura
发明人： Takaaki Shiota , Yasuhiro Oura
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L21/3226 , H01L21/76256
摘要： This method for manufacturing an SOI wafer includes: a step of forming insulating films in a front surface and a mirror-polished rear surface of an active layer wafer; a step of removing the insulating film in the front surface of the active layer wafer; a step of subjecting the active layer wafer to a rapid thermal annealing process; a step of bonding the active layer wafer and a support wafer with the insulating film formed in the rear surface therebetween so as to form a bonded wafer; a step of subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer; and a step of thinning the active layer wafer in the bonded wafer so as to form an SOI layer.

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