专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100009521A1 METHOD OF PRODUCING SEMICONDUCTOR WAFER 审中-公开
标题翻译：生产半导体波长的方法
公开(公告)号：US20100009521A1
公开(公告)日：2010-01-14
申请号：US12501331
申请日：2009-07-10
申请人： Takaaki Shiota , Wataru Itou , Takashi Nakayama
发明人： Takaaki Shiota , Wataru Itou , Takashi Nakayama
IPC分类号： H01L21/322
CPC分类号： H01L21/3225 , H01L21/02008 , Y02P80/30
摘要： There is provided a production method in which the beveling step conducted for preventing the cracking or chipping in a raw wafer during the grinding can be omitted when the raw wafer cut out from a crystalline ingot is processed into a double-side mirror-finished semiconductor wafer and a semiconductor wafer can be obtained cheaply by shortening the whole of the production steps for the semiconductor wafer and decreasing the machining allowance of silicon material in the semiconductor wafer to reduce the kerf loss of the semiconductor material as compared with the conventional method.The method is characterized by comprising a slicing step of cutting out a thin disc-shaped raw wafer from a crystalline ingot; a fixed grain bonded abrasive grinding step of sandwiching the raw wafer between a pair of upper and lower platens each having a pad of fixed grain bonded abrasive to simultaneously grind both surfaces of the raw wafer; a heat treating step of subjecting the raw wafer to a given heat treatment after the fixed grain bonded abrasive grinding step; and a one-side polishing step of polishing each of the both surfaces of the raw wafer after the heat treating step.
摘要翻译：提供了一种制造方法，其中当从晶体块切出的原始晶片被加工成双面镜面半导体晶片时，可以省略在研磨期间防止原始晶片中的开裂或碎裂所进行的斜切步骤通过缩短半导体晶片的整个生产步骤并减少半导体晶片中的硅材料的加工余量，可以廉价地获得半导体晶片，以减少半导体材料的切口损耗。该方法的特征在于包括从晶锭切割薄盘形原始晶片的切片步骤; 将原始晶片夹在一对上下压板之间的固定晶粒粘结磨料研磨步骤，每个上下压板均具有固定颗粒粘合磨料垫，以同时研磨原始晶片的两个表面; 热处理工序，在所述固定晶粒结合磨料研磨工序之后对所述原料晶片进行给定的热处理; 以及在热处理步骤之后对原始晶片的两个表面进行抛光的单面抛光步骤。

2. 发明授权

US07632349B2 Silicon wafer surface defect evaluation method 有权
标题翻译：硅晶片表面缺陷评估方法
公开(公告)号：US07632349B2
公开(公告)日：2009-12-15
申请号：US11467411
申请日：2006-08-25
申请人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
发明人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
IPC分类号： C30B33/00
CPC分类号： H01L22/12
摘要： There is provided a silicon wafer surface defect evaluation method capable of readily detecting a region where small crystal defects exist, the evaluation method comprising: a rapid heat treatment step of a silicon wafer from a silicon single-crystal ingot in an atmosphere which can nitride silicon at a temperature elevating speed of 10 to 150° C./second from a room temperature to temperatures between not lower than 1170° C. and less than a silicon melting point, holding the silicon wafer at the processing temperature for 1 to 120 seconds and then cooling the silicon wafer to the room temperature at a temperature lowering speed of 10 to 100° C./second; and a step of using a surface photo voltage method to calculate a minority carrier diffusion length on the wafer surface, thereby detecting a region on the wafer surface in which small COP's which cannot be detected at least by a particle counter exist.
摘要翻译：提供一种能够容易地检测出存在小晶体缺陷的区域的硅晶片表面缺陷评估方法，该评估方法包括：在能够将氮化硅的气氛中的硅单晶锭的硅晶片的快速热处理步骤以10〜150℃/秒的温度升温速度从室温升温至不低于1170℃，低于硅熔点，将硅晶片在处理温度下保持1〜120秒，然后以10〜100℃/秒的降温速度将硅晶片冷却至室温; 以及使用表面光电压法来计算晶片表面上的少数载流子扩散长度的步骤，从而检测晶片表面上至少存在无法检测到的小的COP的区域。

3. 发明申请

US20070044709A1 Silicon Wafer Surface Defect Evaluation Method 有权
标题翻译：硅晶片表面缺陷评估方法
公开(公告)号：US20070044709A1
公开(公告)日：2007-03-01
申请号：US11467411
申请日：2006-08-25
申请人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
发明人： Wataru Itou , Takeshi Hasegawa , Takaaki Shiota
IPC分类号： C30B15/00 , C30B21/06 , C30B27/02 , C30B28/10 , C30B30/04
CPC分类号： H01L22/12
摘要： There is provided a silicon wafer surface defect evaluation method capable of readily detecting a region where small crystal defects exist. A silicon wafer surface defect evaluation method according to the present invention is characterized by comprising: a rapid heat treatment step of applying a heat treatment to a silicon wafer cut out from a silicon single-crystal ingot in an atmosphere which can nitride silicon at a temperature elevating speed of 10 to 150° C./second from a room temperature to temperatures between not lower than 1170° C. and less than a silicon melting point, holding the silicon wafer at the processing temperature for 1 to 120 seconds and then cooling the silicon wafer to the room temperature at a temperature lowering speed of 10 to 100° C./second; and a step of using a surface photo voltage method to calculate a minority carrier diffusion length on the wafer surface, thereby detecting a region on the wafer surface in which small COP's which cannot be detected at least by a particle counter exist.
摘要翻译：提供了能够容易地检测存在小晶体缺陷的区域的硅晶片表面缺陷评估方法。根据本发明的硅晶片表面缺陷评估方法的特征在于包括：快速热处理步骤，在可以在温度为氮化硅的气氛中从硅单晶锭切出的硅晶片进行热处理将升温速度从室温升温至不低于1170℃至低于硅熔点的温度，将硅晶片在处理温度下保持1至120秒，然后冷却硅晶片以10〜100℃/秒的降温速度至室温; 以及使用表面光电压法来计算晶片表面上的少数载流子扩散长度的步骤，从而检测晶片表面上至少存在无法检测到的小的COP的区域。

4. 发明申请

US20100290971A1 SILICON WAFER AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：硅晶片及其制造方法
公开(公告)号：US20100290971A1
公开(公告)日：2010-11-18
申请号：US12779968
申请日：2010-05-14
申请人： Wataru Itou , Takashi Nakayama , Shigeru Umeno , Hiroaki Taguchi , Yasuo Koike
发明人： Wataru Itou , Takashi Nakayama , Shigeru Umeno , Hiroaki Taguchi , Yasuo Koike
IPC分类号： H01L21/322 , C01B33/021
CPC分类号： H01L21/3225 , C30B15/00 , C30B29/06 , C30B33/005
摘要： It is possible to provide a silicon wafer that as well as being free of COPs and dislocation clusters, has defects (grown-in defects including silicon oxides), which are not overt in an as-grown state, such as OSF nuclei and oxygen precipitate nuclei existing in the PV region, to be vanished or reduced, by adopting a method for producing a silicon wafer, the method comprising the steps of: growing a single crystal silicon ingot by the Czochralski method; cutting a silicon wafer out of the ingot; subjecting the wafer to an RTP at 1,250° C. or more for 10 seconds or more in an oxidizing atmosphere; and removing a grown-in defect region including silicon oxides in the vicinity of wafer surface layer after the RTP.
摘要翻译：可以提供不含COP和位错簇的硅晶片，在生长状态下没有明显的缺陷（包括氧化硅的生长缺陷），例如OSF核和氧沉淀物通过采用硅晶片的制造方法，存在于PV区域中的原子核将被消除或减少，该方法包括以下步骤：通过切克劳斯基法生长单晶硅锭; 从硅锭切出硅晶片; 在氧化气氛中将晶片经受1,250℃或更高10秒钟以上的RTP; 并且在RTP之后去除晶片表面层附近的包含氧化硅的生长缺陷区域。

5. 发明授权

US08231852B2 Silicon wafer and method for producing the same 有权
标题翻译：硅晶片及其制造方法
公开(公告)号：US08231852B2
公开(公告)日：2012-07-31
申请号：US12779968
申请日：2010-05-14
申请人： Wataru Itou , Takashi Nakayama , Shigeru Umeno , Hiroaki Taguchi , Yasuo Koike
发明人： Wataru Itou , Takashi Nakayama , Shigeru Umeno , Hiroaki Taguchi , Yasuo Koike
IPC分类号： C01B33/02 , H01L21/00
CPC分类号： H01L21/3225 , C30B15/00 , C30B29/06 , C30B33/005
摘要： It is possible to provide a silicon wafer that as well as being free of COPs and dislocation clusters, has defects (grown-in defects including silicon oxides), which are not overt in an as-grown state, such as OSF nuclei and oxygen precipitate nuclei existing in the PV region, to be vanished or reduced, by adopting a method for producing a silicon wafer, the method comprising the steps of: growing a single crystal silicon ingot by the Czochralski method; cutting a silicon wafer out of the ingot; subjecting the wafer to an RTP at 1,250° C. or more for 10 seconds or more in an oxidizing atmosphere; and removing a grown-in defect region including silicon oxides in the vicinity of wafer surface layer after the RTP.
摘要翻译：可以提供不含COP和位错簇的硅晶片，在生长状态下没有明显的缺陷（包括氧化硅的生长缺陷），例如OSF核和氧沉淀物通过采用硅晶片的制造方法，存在于PV区域中的原子核将被消除或减少，该方法包括以下步骤：通过切克劳斯基法生长单晶硅锭; 从硅锭切出硅晶片; 在氧化气氛中将晶片经受1,250℃或更高10秒钟以上的RTP; 并且在RTP之后去除晶片表面层附近的包含氧化硅的生长缺陷区域。

6. 发明授权

US5624161A Seat cushion pad supporting construction 失效
标题翻译：座垫垫支撑结构
公开(公告)号：US5624161A
公开(公告)日：1997-04-29
申请号：US365220
申请日：1994-12-28
申请人： Yuuichi Sorimachi , Wataru Itou , Yasushi Yoshino , Teruhiko Yamamoto
发明人： Yuuichi Sorimachi , Wataru Itou , Yasushi Yoshino , Teruhiko Yamamoto
IPC分类号： A47C7/28 , B60N2/70 , A47C7/35
CPC分类号： B60N2/7058 , A47C7/28
摘要： A seat cushion pad supporting construction has a base frame having an opening, and a planar spring deck disposed substantially over the opening. The planar spring deck is formed of a rectangular boundary frame and flexible support members extending front-to-rear between front and rear boundary frame portions of the boundary frame. The flexible support members may be spring steel wires or flexible planar members made of synthetic resin, rubber or fabric. The spring deck is non-resiliently connected at its front boundary frame portion to a front portion of the base frame adjacent the opening to be vertically pivotable with respect to the front base frame portion. The rear boundary frame portion is resiliently connected by tension springs to a rear portion of the base frame adjacent the opening. Optional front and side protruding spring frames are connected to the boundary frame to support the upper legs of an occupant. An optional pivotable linking mechanism supports the front boundary frame portion so that the portion is vertically pivotable with respect to the front base frame portion.
摘要翻译：座垫衬垫支撑结构具有一个具有开口的基座框架和一基本上设置在该开口上的平面弹簧座。平面弹簧甲板由矩形边界框架和在边界框架的前后边界框架部分之间前后延伸的柔性支撑构件形成。柔性支撑构件可以是由合成树脂，橡胶或织物制成的弹簧钢丝或柔性平面构件。弹簧座在其前边界框架部分处非弹性地连接到靠近开口的基座的前部，以相对于前基座框架部分可上下枢转。后边界框架部分通过拉伸弹簧弹性地连接到靠近开口的底架的后部。可选的前侧和侧面突出的弹簧框架连接到边界框架以支撑乘员的大腿。可选的可枢转连接机构支撑前边界框架部分，使得该部分可相对于前基架框架部分竖直枢转。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式