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1. 发明授权

US07133481B2 Synchronization detection apparatus 失效
标题翻译：同步检测装置
公开(公告)号：US07133481B2
公开(公告)日：2006-11-07
申请号：US10311638
申请日：2002-04-05
申请人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Kazuaki Suzuki , Kazuya Ueda
发明人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Kazuaki Suzuki , Kazuya Ueda
IPC分类号： H04L7/00
CPC分类号： H04N5/211 , H04H40/18 , H04L7/042 , H04L7/06 , H04L27/02 , H04N5/08
摘要： An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.
摘要翻译：输入信号DT包含符合ATSC标准的片段同步信号。时钟倍增部分111将时钟CK相乘。可切换取样部112从由倍增时钟定义的多个定时点中选择采样点，并对选择的采样点对输入信号DT进行采样。此外，可切换采样部112在同步未建立状态下将采样点从一个切换到另一个。一旦段同步建立，同步检测装置可以保持同步建立状态，直到现场同步检测失败，或者同步检测装置可以在基于位错误率RT在时间方向上移动同步检测信号之后输出同步检测信号的输入信号。

2. 发明授权

US07054395B2 Automatic gain control for digital demodulation apparatus 失效
标题翻译：数字解调装置的自动增益控制
公开(公告)号：US07054395B2
公开(公告)日：2006-05-30
申请号：US09853682
申请日：2001-05-14
申请人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Hiroaki Ozeki , Kazuya Ueda
发明人： Hiroshi Azakami , Takaaki Konishi , Hisaya Kato , Naoya Tokunaga , Hiroaki Ozeki , Kazuya Ueda
IPC分类号： H04L27/08
CPC分类号： H03G3/3089
摘要： A digital demodulation apparatus automatically controls gain based on a state of receiving a digital modulated signal. The digital demodulation apparatus amplifies a digital modulated signal wave received through the air with the gain automatically controlled so as to have a predetermined amplitude. In the digital demodulation apparatus, a receive level variation detector detects receive level variation, an amount of noise components of the received digital signal wave. A gain controller 15 controls the gain with a receive level variation adaptive control signal based on the detected receive level variation, the amount of noise components.
摘要翻译：数字解调装置根据接收数字调制信号的状态自动控制增益。数字解调装置以自动控制的增益放大通过空气接收的数字调制信号波，以具有预定的幅度。在数字解调装置中，接收电平变化检测器检测接收电平变化，接收的数字信号波的噪声分量的量。增益控制器15基于检测到的接收电平变化，噪声分量的量，利用接收电平变化自适应控制信号来控制增益。

3. 发明授权

US07302021B2 Digital broadcast receiving apparatus 失效
标题翻译：数字广播接收装置
公开(公告)号：US07302021B2
公开(公告)日：2007-11-27
申请号：US09878427
申请日：2001-06-12
申请人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga
发明人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga
IPC分类号： H04L27/08
CPC分类号： H04N5/4446 , H03G3/3068 , H03G3/3089 , H04H40/18 , H04N5/4401 , H04N5/50 , H04N5/52 , H04N21/42607
摘要： In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave with automatically adjusted gain and demodulating the modulated signal wave to a digital signal, a tuner frequency-converts the modulated digital signal wave to generate a first modulated signal. A first automatic gain control amplification unit controls gain of the tuner to make a level of the first modulated signal at a first predetermined level. An A/D converter converts the first modulated signal into a second modulated signal. A demodulator demodulates the second modulated signal to generate a first demodulated digital signal. A second automatic gain control amplifier generates a second demodulated digital signal where frequency fluctuations included in the digital modulated wave are eliminated.
摘要翻译：在一种数字广播接收装置中，用于利用自动调节增益放大接收到的调制数字信号波并将调制信号波解调为数字信号，调谐器对调制数字信号波进行频率转换以产生第一调制信号。第一自动增益控制放大单元控制调谐器的增益使第一调制信号的电平达到第一预定电平。 A / D转换器将第一调制信号转换成第二调制信号。解调器解调第二调制信号以产生第一解调数字信号。第二自动增益控制放大器产生第二解调数字信号，其中消除了数字调制波中包括的频率波动。

4. 发明授权

US06934522B2 Automatic gain control apparatus 失效
标题翻译：自动增益控制装置
公开(公告)号：US06934522B2
公开(公告)日：2005-08-23
申请号：US09886377
申请日：2001-06-22
申请人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga , Hisaya Kato , Hiroaki Ozeki
发明人： Takaaki Konishi , Hiroshi Azakami , Kazuya Ueda , Naoya Tokunaga , Hisaya Kato , Hiroaki Ozeki
IPC分类号： H03G3/20 , H03G1/04 , H04B1/28 , H04B1/06
CPC分类号： H03G1/04 , H04B1/28
摘要： In an automatic gain control amplifier, an RF automatic gain controller controls the gain of a radio frequency signal. A frequency converter frequency-converts the radio frequency signal into an intermediate frequency signal. An IF automatic gain controller controls the gain of the intermediate frequency. A level detector detects a signal level of the gain-controlled intermediate frequency signal, and generates a level signal. An automatic gain control signal generator separately controls, based the level signal, the RF automatic gain controller and the IF automatic gain controller.
摘要翻译：在自动增益控制放大器中，RF自动增益控制器控制射频信号的增益。变频器将射频信号频率转换成中频信号。中频自动增益控制器控制中频增益。电平检测器检测增益控制中频信号的信号电平，并产生电平信号。自动增益控制信号发生器基于电平信号单独控制RF自动增益控制器和IF自动增益控制器。

5. 发明授权

US07333576B2 Digital demodulation device and synchronization detecting method 有权
标题翻译：数字解调装置和同步检测方法
公开(公告)号：US07333576B2
公开(公告)日：2008-02-19
申请号：US10342218
申请日：2003-01-15
申请人： Toshiyuki Satomi , Naoya Tokunaga , Takaaki Konishi , Hisaya Kato
发明人： Toshiyuki Satomi , Naoya Tokunaga , Takaaki Konishi , Hisaya Kato
IPC分类号： H04B1/10 , H03H7/30 , H03H7/40 , H04L7/00 , H04N5/04
CPC分类号： H04N5/455 , H04L7/06 , H04N5/211 , H04N5/4401 , H04N21/4382
摘要： A synchronization error occurs when a DTV signal is distorted on a transmission path and this deteriorates demodulation capability. The digital demodulation device and the synchronization detecting method of the invention can correct the synchronization position when determining that a synchronization error has occurred. A controller receives a center tap coefficient, for example, from a waveform equalizer and compares the coefficient with a given center tap coefficient threshold. If the coefficient is smaller than the threshold, the controller determines that a synchronization detector has made a synchronization error and outputs a control signal. The synchronization detector receiving the control signal re-detects a sync signal included in a received signal, to detect a new correct sync signal and thus correct the synchronization error.
摘要翻译：当DTV信号在传输路径上失真时，发生同步错误，并且这会降低解调能力。本发明的数字解调装置和同步检测方法可以在确定发生同步错误时校正同步位置。控制器例如从波形均衡器接收中心抽头系数，并将系数与给定中心抽头系数阈值进行比较。如果系数小于阈值，则控制器确定同步检测器已经做出同步误差并输出控制信号。接收控制信号的同步检测器重新检测包含在接收信号中的同步信号，以检测新的正确同步信号，从而校正同步误差。

6. 发明授权

US06907064B1 Waveform equalization controller and waveform equalization control method 失效
标题翻译：波形均衡控制器和波形均衡控制方法
公开(公告)号：US06907064B1
公开(公告)日：2005-06-14
申请号：US09698020
申请日：2000-10-30
申请人： Naoya Tokunaga , Kazuya Ueda
发明人： Naoya Tokunaga , Kazuya Ueda
IPC分类号： H04N7/015 , H03H7/30 , H03H7/40 , H03H21/00 , H04L25/03
CPC分类号： H03H21/0012 , H03H2021/0078 , H04L2025/03375 , H04L2025/03617 , H04L2025/03687
摘要： A waveform equalization controller which combines a follow-up property when the distortion is varied and there is a higher convergence speed at the initial operation, and a higher stability at a low C/N time, and which realizes a high performance and a low cost in a waveform equalizer. The waveform equalization controller controls the updating of a tap coefficient, and comprises a waveform equalizer for reducing a transmission line distortion of an input signal based on a LMS algorithm, an error estimation unit for estimating an error signal from an output signal of the waveform equalizer and outputting the error signal, a step size decision unit for generating a step size having an arbitrary size and outputting the step size, and a coefficient updating amount calculation unit for calculating a tap coefficient updating amount based on the error signal, the step size and a tap coefficient updating data.
摘要翻译：一种波形均衡控制器，其在失真变化时具有跟随特性，并且在初始操作时具有较高的收敛速度，并且在低C / N时间具有更高的稳定性，并且实现了高性能和低成本在波形均衡器中。波形均衡控制器控制抽头系数的更新，并且包括用于基于LMS算法减少输入信号的传输线失真的波形均衡器，用于从波形均衡器的输出信号估计误差信号的误差估计单元并输出误差信号;步长决定单元，用于生成具有任意大小的步长并输出步长;以及系数更新量计算单元，用于基于误差信号计算抽头系数更新量，步长和抽头系数更新数据。

7. 发明授权

US06870880B2 Waveform equalization apparatus 失效
标题翻译：波形均衡装置
公开(公告)号：US06870880B2
公开(公告)日：2005-03-22
申请号：US10081718
申请日：2002-02-25
申请人： Naoya Tokunaga , Kazuya Ueda
发明人： Naoya Tokunaga , Kazuya Ueda
IPC分类号： H04N5/14 , G11B20/10 , H04B3/06 , H04L25/03 , H04N5/21 , H03H7/30
CPC分类号： H04L25/03019 , H04L2025/03535
摘要： A waveform equalization apparatus is provided with plural TF (transversal filter) units and plural selectors, and the TF units are connected such that the construction of the whole filter becomes a real component filter when an input signal is a VSB signal while it becomes a complex filter when the input signal is a QAM signal, by switching the inputs of each selector. The waveform equalization apparatus so constructed can waveform-equalize both the VSB signal and the QAM signal, and the circuit scale of the apparatus is reduced.
摘要翻译：波形均衡装置具有多个TF（横向滤波器）单元和多个选择器，并且TF单元被连接，使得当输入信号是VSB信号时，整个滤波器的结构变为实分量滤波器，同时变成复数当输入信号为QAM信号时，通过切换每个选择器的输入进行滤波。这样构成的波形均衡装置能够对VSB信号和QAM信号进行波形均衡，并且减小了装置的电路规模。

8. 发明授权

US07739320B2 Waveform equalizer, waveform equalization method, and integrated circuit 有权
标题翻译：波形均衡器，波形均衡方法和集成电路
公开(公告)号：US07739320B2
公开(公告)日：2010-06-15
申请号：US11130604
申请日：2005-05-17
申请人： Yoshinobu Matsumura , Naoya Tokunaga
发明人： Yoshinobu Matsumura , Naoya Tokunaga
IPC分类号： G06F17/10
CPC分类号： H04L25/03038 , H04L25/03057 , H04L2025/03382 , H04L2025/03477 , H04L2025/0349 , H04L2025/03617 , H04L2025/03687
摘要： A waveform equalizer includes a filter unit, an error estimation unit, a tap coefficient storage unit, and an update amount calculation unit which includes an intermediate calculation unit and an update amount setting unit. Coefficient update amount ΔCi(n) for an ith tap is calculated according to an equation ΔCi(n)=αi(n)×μ×e(n)×x*(n−i) with the multiplication by αi(n) being performed by the update amount setting unit. Here, 0
摘要翻译：波形均衡器包括滤波器单元，误差估计单元，抽头系数存储单元和包括中间计算单元和更新量设置单元的更新量计算单元。根据等式＆Dgr计算第i个抽头的系数更新量和Dgr; Ci（n）; Ci（n）=αi（n）×μ×e（n）×x *（n-i）乘以αi （n）由更新量设定单元执行。这里，0 <αi（n）＆nlE; 1和αi（n）是与Ci（n-1）单调增加的函数f（Ci（n-1））。

9. 发明授权

US06453394B2 Memory interface device and memory address generation device 有权
标题翻译：存储器接口设备和存储器地址生成设备
公开(公告)号：US06453394B2
公开(公告)日：2002-09-17
申请号：US09165785
申请日：1998-10-02
申请人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
发明人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
IPC分类号： G06F1200
CPC分类号： G06F9/345 , G06F13/1673 , H04N19/423 , H04N19/61
摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
摘要翻译：本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括8个多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中。控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号的输出缓冲区。

10. 发明授权

US06393564B1 Decrypting device 失效
标题翻译：解密设备
公开(公告)号：US06393564B1
公开(公告)日：2002-05-21
申请号：US09163257
申请日：1998-09-29
申请人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
发明人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
IPC分类号： G06F124
CPC分类号： H04L9/0877 , H04L2209/08
摘要： The decrypting device of this invention includes: a decrypting key generation circuit for generating a decrypting key based on first decrypting key information and second decrypting key information; and a decrypting circuit for decrypting encrypted information using the decrypting key, wherein the first decrypting key information is input from outside the decrypting device, and the second decrypting key information is stored inside the decrypting device.
摘要翻译：本发明的解密装置包括：解密密钥生成电路，用于基于第一解密密钥信息和第二解密密钥信息生成解密密钥; 以及解密电路，用于使用解密密钥对加密信息进行解密，其中，从解密装置外部输入第一解密密钥信息，第二解密密钥信息存储在解密装置内。

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