专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06732252B2 Memory interface device and memory address generation device 有权
标题翻译：存储器接口设备和存储器地址生成设备
公开(公告)号：US06732252B2
公开(公告)日：2004-05-04
申请号：US10195975
申请日：2002-07-16
申请人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
发明人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
IPC分类号： G06F1200
CPC分类号： G06F9/345 , G06F13/1673 , H04N19/423 , H04N19/61
摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
摘要翻译：本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中。控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号的输出缓冲区。

2. 发明授权

US06453394B2 Memory interface device and memory address generation device 有权
标题翻译：存储器接口设备和存储器地址生成设备
公开(公告)号：US06453394B2
公开(公告)日：2002-09-17
申请号：US09165785
申请日：1998-10-02
申请人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
发明人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
IPC分类号： G06F1200
CPC分类号： G06F9/345 , G06F13/1673 , H04N19/423 , H04N19/61
摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
摘要翻译：本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括8个多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中。控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号的输出缓冲区。

3. 发明授权

US06353460B1 Television receiver, video signal processing device, image processing device and image processing method 失效
标题翻译：电视接收机，视频信号处理装置，图像处理装置及图像处理方法
公开(公告)号：US06353460B1
公开(公告)日：2002-03-05
申请号：US09162740
申请日：1998-09-29
申请人： Kenta Sokawa , Kazuki Ninomiya , Yoichiro Miki , Naoya Tokunaga , Masahiro Tani , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama
发明人： Kenta Sokawa , Kazuki Ninomiya , Yoichiro Miki , Naoya Tokunaga , Masahiro Tani , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama
IPC分类号： H04N327
CPC分类号： H04N7/0122 , H04N5/45 , H04N5/46 , H04N5/907 , H04N7/01 , H04N21/4316 , H04N21/440218 , H04N21/4622
摘要： The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.
摘要翻译：包括能够显示具有本发明的预定显示器的视频信号的显示装置的电视接收机包括：多个视频信号源; 选择电路，用于选择从多个视频信号源输出的多个视频信号之一; 以及用于将由选择电路选择的视频信号的格式转换为预定显示格式的图像处理器，其中从处理器输出的视频信号被提供给显示装置。

4. 发明授权

US06393564B1 Decrypting device 失效
标题翻译：解密设备
公开(公告)号：US06393564B1
公开(公告)日：2002-05-21
申请号：US09163257
申请日：1998-09-29
申请人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
发明人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
IPC分类号： G06F124
CPC分类号： H04L9/0877 , H04L2209/08
摘要： The decrypting device of this invention includes: a decrypting key generation circuit for generating a decrypting key based on first decrypting key information and second decrypting key information; and a decrypting circuit for decrypting encrypted information using the decrypting key, wherein the first decrypting key information is input from outside the decrypting device, and the second decrypting key information is stored inside the decrypting device.
摘要翻译：本发明的解密装置包括：解密密钥生成电路，用于基于第一解密密钥信息和第二解密密钥信息生成解密密钥; 以及解密电路，用于使用解密密钥对加密信息进行解密，其中，从解密装置外部输入第一解密密钥信息，第二解密密钥信息存储在解密装置内。

5. 发明授权

US6128733A Program loading method and apparatus 有权
标题翻译：程序加载方法和装置
公开(公告)号：US6128733A
公开(公告)日：2000-10-03
申请号：US165574
申请日：1998-10-02
申请人： Hiroshi Miyaguchi , Naoya Tokunaga
发明人： Hiroshi Miyaguchi , Naoya Tokunaga
IPC分类号： G06F9/06 , G06F9/445 , G06F15/177
CPC分类号： G06F9/445
摘要： A method for loading of program data with high speed and efficiency along with eliminating the need for software modification even if changes occur in the storage addresses and data length of the program data stored in the program memory. In order to load program data in a rewritable manner into a number of functional circuits FC0, FC1, . . . , FCn operating in accordance with the supplied program data, a program memory, for example, a ROM 10, a program loader 12, and program designating apparatus, for example, a microprocessor 14, are provided in the system. In the ROM 10, multiple address pointers are stored in specified storage areas, and corresponding sets of program data are stored in the storage locations indicated by the address pointers in such a manner that a first set of program data is stored in the specified storage area which utilizes the address corresponding to the first address pointer as the start storage address, and a second set of program data is stored in the specified storage area which utilizes the address corresponding to the second address pointer as the start storage address.
摘要翻译：一种用于以高速度和高效率加载程序数据的方法，即使存储在程序存储器中的程序数据的存储地址和数据长度发生变化也不需要软件修改。为了将程序数据以可重写的方式加载到多个功能电路FC0，FC1，...中。。。，根据提供的程序数据操作的FCn，在系统中提供程序存储器，例如ROM 10，程序加载器12和程序指定装置，例如微处理器14。在ROM10中，多个地址指针被存储在指定的存储区域中，并且相应的程序数据组被存储在由地址指针指示的存储位置中，使得第一组程序数据被存储在指定的存储区域其利用与第一地址指针相对应的地址作为开始存储地址，并且将第二组程序数据存储在利用与第二地址指针相对应的地址作为起始存储地址的指定存储区域中。

6. 发明授权

US6047366A Single-instruction multiple-data processor with input and output registers having a sequential location skip function 失效
标题翻译：具有输入和输出寄存器的单指令多数据处理器具有顺序位置跳过功能
公开(公告)号：US6047366A
公开(公告)日：2000-04-04
申请号：US993803
申请日：1997-12-18
申请人： Kazuhiro Ohara , Hiroshi Miyaguchi , Yuji Yaguchi
发明人： Kazuhiro Ohara , Hiroshi Miyaguchi , Yuji Yaguchi
IPC分类号： G06F15/80 , G06F15/76
CPC分类号： G06F15/8015
摘要： A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.
摘要翻译：单指令多数据（SIMD）处理器（10），其包含用于视频数据的水平缩放的特征。处理器（10）具有数据输入寄存器（11），其可操作以将输入数据字存储在数据输入寄存器（11）中的顺序位置，并将输入数据字传送到处理元件阵列。处理器（10）还具有输出数据寄存器（16），其可操作以从处理元件阵列接收数据输出字，并从所述输出数据阵列的顺序位置输出所述数据输出字。输入到处理器的输入跳过信号导致顺序数据写入操作跳过输入数据寄存器的位置，而到处理器的输出跳过信号导致顺序数据读取操作跳过输出数据寄存器的位置。

7. 发明授权

US06763450B1 Processor 有权
标题翻译：处理器
公开(公告)号：US06763450B1
公开(公告)日：2004-07-13
申请号：US09680609
申请日：2000-10-06
申请人： Hiroshi Miyaguchi , Tsuyoshi Akiyama , Hidetoshi Onuma
发明人： Hiroshi Miyaguchi , Tsuyoshi Akiyama , Hidetoshi Onuma
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/325
摘要： The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP core 12 of this SVP (Scan-line Video Processor) 10 is made up of a three layer construction of the data input register (DIR) 16, the SIMD type digital signal processing unit 18, and the data output register (DOR) 20. The SIMD type digital signal processing unit 18 comprises a parallel arranged (connected) number of processing elements (PE0 to PEN−1) (for example, 864 units) equal to the number of pixels N on one horizontal scan line. The instruction generator (IG) 14, because the SVP core 12 operates as an SIMD parallel processor, internally houses a RAM or ROM program memory that holds the desired program. The program stored in program memory contains not only the instructions (SIMD instruction) for the processing elements (PE0 to PEN−1) of the processing unit 18, but also such instructions (IG instruction) as jump, subroutine call, hardware interrupt, and the like. In this SVP 10, when an IG instruction is read from the program memory while the repetitive processing of an SIMD instruction is being conducted in the SVP core 12, the pertinent IG instruction is executed in parallel with the repetitive processing of the pertinent SIMD instruction.
摘要翻译：本发明的目的是提高在多个时钟周期内重复执行一个指令的系统的处理效率。该SVP（扫描线视频处理器）10的SVP核心12由数据输入寄存器（DIR）16，SIMD型数字信号处理单元18和数据输出寄存器（DOR）的三层结构组成， SIMD型数字信号处理单元18包括与一个水平扫描线上的像素数N相等的并行布置（连接）数量的处理元件（PE0至PEN-1）（例如，864单位）。指令发生器（IG）14，由于SVP核心12作为SIMD并行处理器操作，所以内部容纳保存所需程序的RAM或ROM程序存储器。存储在程序存储器中的程序不仅包含处理单元18的处理元件（PE0至PEN-1）的指令（SIMD指令），还包含跳转，子程序调用，硬件中断和类似。在该SVP10中，当在SVP核心12中进行SIMD指令的重复处理时从程序存储器读取IG指令时，与相关的SIMD指令的重复处理并行地执行相关的IG指令。

8. 发明授权

US5210836A Instruction generator architecture for a video signal processor controller 失效
标题翻译：视频信号处理器控制器的指令生成器架构
公开(公告)号：US5210836A
公开(公告)日：1993-05-11
申请号：US421500
申请日：1989-10-13
申请人： Jim Childers , Peter Reinecke , Moo-Taek Chung , Hiroshi Miyaguchi
发明人： Jim Childers , Peter Reinecke , Moo-Taek Chung , Hiroshi Miyaguchi
IPC分类号： F02B75/02 , G06F15/80 , G06T1/20
CPC分类号： G06T1/20 , G06F15/8007 , F02B2075/027
摘要： A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.
摘要翻译：具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置。处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且能够对视频信号进行实时数字处理。在视频应用中，提供了包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路的数据输入控制电路。

9. 发明授权

US5600582A Programmable horizontal line filter implemented with synchronous vector processor 失效
标题翻译：可编程水平线滤波器采用同步矢量处理器实现
公开(公告)号：US5600582A
公开(公告)日：1997-02-04
申请号：US222775
申请日：1994-04-05
申请人： Hiroshi Miyaguchi
发明人： Hiroshi Miyaguchi
IPC分类号： G06F15/80 , G06F17/17 , H03H17/06 , G06F15/31
CPC分类号： H03H17/0664 , G06F15/8092 , G06F17/175
摘要： A synchronous vector processor (SVP) (30) is provided to realize a horizontal decimation filter by processing in input value through a plurality of parallel processing elements (40). A plurality of input pixel values (80) representing a horizontal line of information in a video display are input to a data input register (DIR) (31) of the SVP (30). Each of the processing elements (40) is associated with a filter output and is operable to perform all calculations necessary to realize a multi-tap filter structure for the associated output. This is achieved by first increasing the frequency of the input signal by inserting zeros therein and then performing a number of multiplications and additions to generate an output value for that processing element, this realizing an interpolation FIR filter algorithm. The finite impulse response (FIR) filter algorithm is defined by predetermined filter coefficients stored in a constant generator (71d). Each of the processing elements are utilized to multiply a plurality of near-neighbor input values with FIR filter coefficients that are obtained from a constant generator (71d). The resulting sum for each of the processing elements is then input to the a data output register (DOR) (16) as the filter output. The output of the SVP (30) is then input to line memory (90) that is operable to decimate the output of select ones of the processing elements of the SVP (30). This rearranges the outputs to decrease the number of output pixels for each line relative to the number of input pixels for each line.
摘要翻译：提供同步向量处理器（SVP）（30）以通过多个并行处理元件（40）处理输入值来实现水平抽取滤波器。表示视频显示中的水平线信息的多个输入像素值（80）被输入到SVP（30）的数据输入寄存器（DIR）（31）。每个处理元件（40）与滤波器输出相关联，并且可操作以执行为相关输出实现多抽头滤波器结构所必需的所有计算。这通过首先通过在其中插入零来增加输入信号的频率，然后执行多个乘法和加法来产生该处理元件的输出值，这实现了一种插值FIR滤波算法来实现。有限脉冲响应（FIR）滤波算法由存储在常数发生器（71d）中的预定滤波器系数定义。每个处理元件用于将多个近邻输入值与从常数发生器（71d）获得的FIR滤波器系数相乘。然后将每个处理元件的结果和作为滤波器输出输入到数据输出寄存器（DOR）（16）。然后，SVP（30）的输出被输入到行存储器（90），该存储器可操作以抽取SVP（30）的选择的处理元件的输出。这将重新排列输出，以减少每一行相对于每行输入像素数的输出像素数。

10. 发明授权

US5408673A Circuit for continuous processing of video signals in a synchronous vector processor and method of operating same 失效
标题翻译：用于在同步向量处理器中连续处理视频信号的电路及其操作方法
公开(公告)号：US5408673A
公开(公告)日：1995-04-18
申请号：US35519
申请日：1993-03-22
申请人： Jim Childers , Hiroshi Miyaguchi
发明人： Jim Childers , Hiroshi Miyaguchi
IPC分类号： F02B75/02 , G06F15/80 , G06F15/16 , G06F15/06
CPC分类号： G06F15/8092 , G06F15/8015 , F02B2075/027
摘要： A data processing apparatus includes a dual port data input register, first and second sequential ring counters, first and second register files, first and second data transfer circuits, a dual port data output register and N single bit processing elements. The dual port data input register has an M bit wide input port and an N bit wide output port. The first sequential ring counter cyclically selects one column of the data input register for input. The first data transfer circuit has a plurality of input segments, which are subsets of consecutive columns of the data input register. The first data transfer circuit transfers data from a selected row of the data input register to a selected row of the first register file for all columns of each input segment in a repetitive sequence of consecutive input segments in synchronism with said first sequential ring counter. The dual port data output register, the second register file, the second sequential ring counter and the second data transfer circuit are similarly organized to output data. Each of the N single bit processing elements is connected to a predetermined column of the first and second register files and capable of data processing operations under program control including data transfer to and from selected rows of said predetermined column of said first and second register files.
摘要翻译：数据处理装置包括双端口数据输入寄存器，第一和第二顺序环形计数器，第一和第二寄存器文件，第一和第二数据传输电路，双端口数据输出寄存器和N个单个位处理元件。双端口数据输入寄存器具有M位宽的输入端口和N位宽的输出端口。第一个顺序环形计数器循环选择数据输入寄存器的一列进行输入。第一数据传送电路具有多个输入段，它们是数据输入寄存器的连续列的子集。第一数据传送电路与所述第一顺序环形计数器同步地将数据从数据输入寄存器的所选行传送到连续输入段的重复序列中的每个输入段的所有列的选定行。类似地，将双端口数据输出寄存器，第二寄存器文件，第二顺序环形计数器和第二数据传送电路组织成输出数据。 N个单位处理单元中的每一个连接到第一和第二寄存器堆的预定列，并且能够进行程序控制下的数据处理操作，包括从所述第一和第二寄存器堆的所述预定列的选定行的数据传送。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式