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1. 发明授权

US06353460B1 Television receiver, video signal processing device, image processing device and image processing method 失效
标题翻译：电视接收机，视频信号处理装置，图像处理装置及图像处理方法
公开(公告)号：US06353460B1
公开(公告)日：2002-03-05
申请号：US09162740
申请日：1998-09-29
申请人： Kenta Sokawa , Kazuki Ninomiya , Yoichiro Miki , Naoya Tokunaga , Masahiro Tani , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama
发明人： Kenta Sokawa , Kazuki Ninomiya , Yoichiro Miki , Naoya Tokunaga , Masahiro Tani , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama
IPC分类号： H04N327
CPC分类号： H04N7/0122 , H04N5/45 , H04N5/46 , H04N5/907 , H04N7/01 , H04N21/4316 , H04N21/440218 , H04N21/4622
摘要： The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.
摘要翻译：包括能够显示具有本发明的预定显示器的视频信号的显示装置的电视接收机包括：多个视频信号源; 选择电路，用于选择从多个视频信号源输出的多个视频信号之一; 以及用于将由选择电路选择的视频信号的格式转换为预定显示格式的图像处理器，其中从处理器输出的视频信号被提供给显示装置。

2. 发明授权

US5860084A Method for reading data in a memory cell 失效
标题翻译：用于读取存储器单元中的数据的方法
公开(公告)号：US5860084A
公开(公告)日：1999-01-12
申请号：US862573
申请日：1997-05-23
申请人： Yuji Yaguchi
发明人： Yuji Yaguchi
IPC分类号： G06F9/38 , G06F15/80 , G06T1/20 , G11C7/10 , G06F12/00
CPC分类号： G11C7/1087 , G06F15/8015 , G06F9/3867 , G11C7/1051 , G11C7/1072 , G11C7/1078
摘要： A method of reading a memory cell containing an access transistor, a word line and a memory storage for holding information. The access transistor having a control terminal is connected to the word line. The memory storage is connected to the access transistor and thereby to a sense amplifier through a bit line. The access transistor, operating in a conductive state, is responsive to the word line. The bit line is precharged to an intermediate voltage level greater than a low threshold level and less than an upper limit level. The bit line is discharged from the intermediate voltage level to produce a low voltage level in a prescribed time if the memory storage holds memory information of a first state. The bit line is charged to approximately the upper limit level in the prescribed time if the memory storage holds memory information of a second state. The voltage of the bit line is determined by the sense amplifier after the prescribed time so that the memory information is read.
摘要翻译：一种读取包含存取晶体管，字线和存储信息的存储器的存储单元的方法。具有控制端子的存取晶体管连接到字线。存储器存储器连接到存取晶体管，从而通过位线连接到读出放大器。在导通状态下工作的存取晶体管响应于字线。位线被预充电到大于低阈值电平并小于上限电平的中间电压电平。如果存储器存储器保持第一状态的存储器信息，则位线从中间电压电平放电以在规定时间内产生低电压电平。如果存储器存储器保持第二状态的存储器信息，则位线在规定时间内被充电到大约上限级别。位线的电压由规定时间之后的读出放大器决定，从而读取存储器信息。

3. 发明授权

US06732252B2 Memory interface device and memory address generation device 有权
标题翻译：存储器接口设备和存储器地址生成设备
公开(公告)号：US06732252B2
公开(公告)日：2004-05-04
申请号：US10195975
申请日：2002-07-16
申请人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
发明人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
IPC分类号： G06F1200
CPC分类号： G06F9/345 , G06F13/1673 , H04N19/423 , H04N19/61
摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
摘要翻译：本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中。控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号的输出缓冲区。

4. 发明授权

US6047366A Single-instruction multiple-data processor with input and output registers having a sequential location skip function 失效
标题翻译：具有输入和输出寄存器的单指令多数据处理器具有顺序位置跳过功能
公开(公告)号：US6047366A
公开(公告)日：2000-04-04
申请号：US993803
申请日：1997-12-18
申请人： Kazuhiro Ohara , Hiroshi Miyaguchi , Yuji Yaguchi
发明人： Kazuhiro Ohara , Hiroshi Miyaguchi , Yuji Yaguchi
IPC分类号： G06F15/80 , G06F15/76
CPC分类号： G06F15/8015
摘要： A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.
摘要翻译：单指令多数据（SIMD）处理器（10），其包含用于视频数据的水平缩放的特征。处理器（10）具有数据输入寄存器（11），其可操作以将输入数据字存储在数据输入寄存器（11）中的顺序位置，并将输入数据字传送到处理元件阵列。处理器（10）还具有输出数据寄存器（16），其可操作以从处理元件阵列接收数据输出字，并从所述输出数据阵列的顺序位置输出所述数据输出字。输入到处理器的输入跳过信号导致顺序数据写入操作跳过输入数据寄存器的位置，而到处理器的输出跳过信号导致顺序数据读取操作跳过输出数据寄存器的位置。

5. 发明授权

US06453394B2 Memory interface device and memory address generation device 有权
标题翻译：存储器接口设备和存储器地址生成设备
公开(公告)号：US06453394B2
公开(公告)日：2002-09-17
申请号：US09165785
申请日：1998-10-02
申请人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
发明人： Yoichiro Miki , Masahiro Tani , Kazuki Ninomiya , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi , Yuji Yaguchi , Tsuyoshi Akiyama , Kenya Adachi
IPC分类号： G06F1200
CPC分类号： G06F9/345 , G06F13/1673 , H04N19/423 , H04N19/61
摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
摘要翻译：本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括8个多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中。控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号的输出缓冲区。

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