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1. 发明授权

US5550395A Semiconductor device and process of producing same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5550395A
公开(公告)日：1996-08-27
申请号：US376082
申请日：1995-01-20
申请人： Taiji Ema , Toshimi Ikeda
发明人： Taiji Ema , Toshimi Ikeda
IPC分类号： H01L21/8244 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/105 , H01L27/10817 , H01L27/11 , H01L27/1116 , H01L28/86
摘要： A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covers the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括具有存储单元区域的半导体衬底和围绕存储单元区域的电路区域，其间插入有边界区域。第一导电层覆盖存储单元区域并延伸到边界区域上。第一绝缘层覆盖周围电路区域和第一导电层的延伸部分的一部分。第二绝缘层覆盖第一绝缘层和第一导电层。通过第一绝缘层和第二绝缘层形成通孔。第二导电层经由通孔与另一导电层电连接，并从存储单元区域延伸到周围电路区域。还公开了制造半导体器件的工艺。

2. 发明授权

US5661340A Dynamic random access memory having a stacked fin capacitor with reduced fin thickness 失效
标题翻译：动态随机存取存储器，其具有减小翅片厚度的堆叠鳍式电容器
公开(公告)号：US5661340A
公开(公告)日：1997-08-26
申请号：US141691
申请日：1993-10-26
申请人： Taiji Ema , Masaaki Higashitani , Toshimi Ikeda , Michiari Kawano , Hiroshi Nomura , Masaya Katayama , Masahiro Kuwamura
发明人： Taiji Ema , Masaaki Higashitani , Toshimi Ikeda , Michiari Kawano , Hiroshi Nomura , Masaya Katayama , Masahiro Kuwamura
IPC分类号： H01L21/8242 , H01L27/108 , H01L23/02 , H01L21/265
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.
摘要翻译：一种用于制造动态随机存取存储器的方法，包括以下步骤：在半导体衬底中形成扩散区，在半导体衬底上提供绝缘层，在绝缘层上形成接触孔，露出接触孔处的扩散区，沉积在绝缘层上形成非晶状态的半导体层，使得半导体层经由接触孔与暴露的扩散区域形成紧密接触，构图半导体层以形成电容器电极，在电容器电极上沉积电介质膜，使得所述电介质膜覆盖电容器电极; 以及沉积半导体材料以形成相对的电极，使得相对电极将电容器电极埋在下面，同时与覆盖电容器电极的电介质膜形成紧密接触。

3. 发明授权

US5688712A Process for producing a semiconductor device 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US5688712A
公开(公告)日：1997-11-18
申请号：US643938
申请日：1996-05-07
申请人： Taiji Ema , Toshimi Ikeda
发明人： Taiji Ema , Toshimi Ikeda
IPC分类号： H01L21/8244 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L21/70
CPC分类号： H01L27/105 , H01L27/10817 , H01L27/11 , H01L27/1116 , H01L28/86
摘要： A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covering the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括具有存储单元区域的半导体衬底和围绕存储单元区域的电路区域，其间插入有边界区域。第一导电层覆盖存储单元区域并延伸到边界区域上。第一绝缘层覆盖周围电路区域和第一导电层的延伸部分的一部分。覆盖第一绝缘层和第一导电层的第二绝缘层。通过第一绝缘层和第二绝缘层形成通孔。第二导电层经由通孔与另一导电层电连接，并从存储单元区域延伸到周围电路区域。还公开了制造半导体器件的工艺。

4. 发明授权

US5591659A Process of producing a semiconductor device in which a height difference between a memory cell area and a peripheral area is eliminated 失效
标题翻译：制造其中消除了存储单元区域和外围区域之间的高度差的半导体器件的工艺
公开(公告)号：US5591659A
公开(公告)日：1997-01-07
申请号：US318261
申请日：1994-10-05
申请人： Taiji Ema , Toshimi Ikeda
发明人： Taiji Ema , Toshimi Ikeda
IPC分类号： H01L21/8242 , H01L21/8244 , H01L27/105 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L28/86
摘要： A semiconductor device comprising: a semiconductor substrate having a memory cell area containing a memory cell composed of a capacitor element, and a peripheral circuit area containing a peripheral circuit for controlling the memory cell; an insulating layer covering the peripheral circuit area and being absent in the memory cell area; protective layers effective in etching of the insulating layer and covering the top surfaces and side surfaces of word line conductor patters and bit line conductor patterns in the memory cell area; a contact hole having a circumference defined by one of the protective layers that covers side surfaces of the word line conductor patterns in the memory cell area, the contact hole extending to a diffused region in the semiconductor substrate; and a storage electrode of the capacitor element being connected to the diffused region through the contact hole. A process of producing the semiconductor device is also disclosed.
摘要翻译：一种半导体器件，包括：具有包含由电容器元件构成的存储单元的存储单元区域的半导体衬底和包含用于控制存储单元的外围电路的外围电路区域; 覆盖外围电路区域并且不存在于存储单元区域中的绝缘层; 保护层有效地蚀刻绝缘层并覆盖存储单元区域中的字线导体图案和位线导体图案的顶表面和侧表面; 接触孔，其具有由覆盖所述存储单元区域中的字线导体图案的侧表面的保护层之一限定的圆周，所述接触孔延伸到所述半导体衬底中的扩散区域; 并且电容器元件的存储电极通过接触孔连接到扩散区域。还公开了制造半导体器件的工艺。

5. 发明授权

US08907430B2 Semiconductor device and manufacturing method of semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US08907430B2
公开(公告)日：2014-12-09
申请号：US12599431
申请日：2009-11-09
申请人： Akihiro Usujima , Junichi Ariyoshi , Taiji Ema
发明人： Akihiro Usujima , Junichi Ariyoshi , Taiji Ema
IPC分类号： H01L27/088 , H01L27/115 , H01L21/28 , H01L21/8234 , H01L27/105 , H01L29/788
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/7881
摘要： A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.
摘要翻译：半导体器件包括存储晶体管，其包括设置在外部的第一侧壁绝缘膜和第二侧壁绝缘膜; 包括具有与第一侧壁绝缘膜相同组成的第三侧壁绝缘膜的高压晶体管，以及具有与第二侧壁绝缘膜相同组成的第四侧壁绝缘膜，第四侧壁绝缘膜设置在外部; 以及包括具有与第二和第四侧壁绝缘膜相同组成的第五侧壁绝缘膜的低压晶体管。存储晶体管，高压晶体管和低压晶体管设置在同一基板上。低压晶体管的总侧壁间隔物宽度小于高压晶体管的相对于第三侧壁绝缘膜的厚度。

6. 发明授权

US08741727B2 Method of manufacturing semiconductor device capable of reducing a size of the semiconductor device 有权
标题翻译：能够减小半导体器件的尺寸的半导体器件的制造方法
公开(公告)号：US08741727B2
公开(公告)日：2014-06-03
申请号：US13106129
申请日：2011-05-12
申请人： Junichi Ariyoshi , Taiji Ema , Toru Anezaki
发明人： Junichi Ariyoshi , Taiji Ema , Toru Anezaki
IPC分类号： H01L21/02
CPC分类号： H01L27/11526 , H01L21/823462 , H01L21/823857 , H01L27/0629 , H01L27/105 , H01L27/11546 , H01L28/60
摘要： A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.
摘要翻译：一种制造半导体器件的方法包括在第一区域形成闪存单元，在第二区域形成电容器的第一电极，形成第一氧化硅膜，氮化硅膜和第二氧化硅膜作为第二绝缘膜，在第一电极的部分区域中去除氮化硅膜和第二氧化硅膜，在第三区域中湿蚀刻第一绝缘膜和第二绝缘膜，形成第二绝缘膜的第二电极电容器，并且蚀刻并去除部分区域中的第一氧化硅膜。

7. 发明授权

US08415215B2 Method of manufacturing semiconductor device with multiple implantation steps 有权
标题翻译：制造具有多个注入步骤的半导体器件的方法
公开(公告)号：US08415215B2
公开(公告)日：2013-04-09
申请号：US13111280
申请日：2011-05-19
申请人： Junichi Ariyoshi , Taiji Ema
发明人： Junichi Ariyoshi , Taiji Ema
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/8236 , H01L21/425
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823857
摘要： A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.
摘要翻译：一种制造半导体器件的方法包括：分别在第一至第三区域中形成第一至第三栅电极; 在暴露所述第一和第三区域的同时形成覆盖所述第二区域的第一掩模图案; 通过使用第一掩模图案作为掩模通过离子注入形成p型源极漏极延伸和p型空穴区域; 通过使用第一掩模图案作为掩模的离子注入形成n型源极漏极延伸; 形成覆盖所述第一和第三区域同时暴露所述第二区域的第二掩模图案; 以及通过将第二掩模图案用作掩模将铟的离子注入到硅衬底中形成p型袋区域。

8. 发明授权

US08377783B2 Method for reducing punch-through in a transistor device 有权
标题翻译：降低晶体管器件穿透的方法
公开(公告)号：US08377783B2
公开(公告)日：2013-02-19
申请号：US12895695
申请日：2010-09-30
申请人： Lucian Shifren , Taiji Ema
发明人： Lucian Shifren , Taiji Ema
IPC分类号： H01L21/336
CPC分类号： H01L29/1083 , H01L27/0921
摘要： Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped layer in the stop layer of lesser depth than the stop layer. The stop layer has a lower concentration of impurities than the doped layer in order to prevent punch-through without increasing junction leakage.
摘要翻译：在晶体管器件中的穿通通过在注入区域中形成阱层而减少，在阱层中形成比阱层更深的阱层中的阻挡层，以及在比止蚀层更深的深度的阻挡层中形成掺杂层层。阻止层的杂质浓度比掺杂层低，以防止穿通而不增加结漏电。

9. 发明申请

US20120223391A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120223391A1
公开(公告)日：2012-09-06
申请号：US13343078
申请日：2012-01-04
申请人： Kazushi Fujita , Taiji Ema , Hiroyuki Ogawa
发明人： Kazushi Fujita , Taiji Ema , Hiroyuki Ogawa
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857 , H01L21/823892 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.
摘要翻译：半导体器件包括：第一晶体管，包括形成在半导体衬底的第一区域中的第一导电类型的第一杂质层;形成在第一杂质层上方的第一外延半导体层;形成在第一外延半导体上方的第一栅极绝缘膜; 以及形成在所述第一栅极绝缘膜上方的第一栅电极，以及形成在所述半导体衬底的第二区域中的包括所述第二导电类型的第二杂质层的第二晶体管，形成在所述第二杂质层上方的第二外延半导体层并且具有不同于第一外延半导体层的厚度的第二栅极绝缘膜，形成在第二外延半导体层上方并具有与第一栅极绝缘膜相同的膜厚度的第二栅极绝缘膜和形成在第二栅极之上的第二栅电极绝缘膜。

10. 发明授权

US08158483B2 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08158483B2
公开(公告)日：2012-04-17
申请号：US13075625
申请日：2011-03-30
申请人： Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L21/336
CPC分类号： H01L21/823857 , H01L21/823892 , H01L27/0629
摘要： A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
摘要翻译：半导体器件制造方法包括：在半导体衬底中形成具有1以上的纵横比的隔离区域，形成栅极绝缘膜，形成硅栅电极和硅电阻元件，在栅电极上形成侧壁间隔物，用磷和第二有源区掺杂第一有源区，通过离子注入掺杂p型杂质的电阻元件，在500℃或更低的温度下形成自对准硅化物块，沉积覆盖自对准硅化物块的金属层，并选择性地形成金属硅化物层。该方法可以进一步包括：形成厚和薄的栅极绝缘膜，并且执行不穿透厚栅极绝缘膜的第一导电类型的离子的注入和相反导电类型的离子的倾斜注入也穿透厚栅极绝缘膜在形成侧壁间隔物之前。

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