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1. 发明授权

US08907430B2 Semiconductor device and manufacturing method of semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US08907430B2
公开(公告)日：2014-12-09
申请号：US12599431
申请日：2009-11-09
申请人： Akihiro Usujima , Junichi Ariyoshi , Taiji Ema
发明人： Akihiro Usujima , Junichi Ariyoshi , Taiji Ema
IPC分类号： H01L27/088 , H01L27/115 , H01L21/28 , H01L21/8234 , H01L27/105 , H01L29/788
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/7881
摘要： A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.
摘要翻译：半导体器件包括存储晶体管，其包括设置在外部的第一侧壁绝缘膜和第二侧壁绝缘膜; 包括具有与第一侧壁绝缘膜相同组成的第三侧壁绝缘膜的高压晶体管，以及具有与第二侧壁绝缘膜相同组成的第四侧壁绝缘膜，第四侧壁绝缘膜设置在外部; 以及包括具有与第二和第四侧壁绝缘膜相同组成的第五侧壁绝缘膜的低压晶体管。存储晶体管，高压晶体管和低压晶体管设置在同一基板上。低压晶体管的总侧壁间隔物宽度小于高压晶体管的相对于第三侧壁绝缘膜的厚度。

2. 发明申请

US20100308420A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20100308420A1
公开(公告)日：2010-12-09
申请号：US12599431
申请日：2007-07-31
申请人： Akihiro Usujima , Junichi Ariyoshi , Taiji Ema
发明人： Akihiro Usujima , Junichi Ariyoshi , Taiji Ema
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/40114 , H01L29/7881
摘要： A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.
摘要翻译：半导体器件包括存储晶体管，其包括设置在外部的第一侧壁绝缘膜和第二侧壁绝缘膜; 包括具有与第一侧壁绝缘膜相同组成的第三侧壁绝缘膜的高压晶体管，以及具有与第二侧壁绝缘膜相同组成的第四侧壁绝缘膜，第四侧壁绝缘膜设置在外部; 以及包括具有与第二和第四侧壁绝缘膜相同组成的第五侧壁绝缘膜的低压晶体管。存储晶体管，高压晶体管和低压晶体管设置在同一基板上。低压晶体管的总侧壁间隔物宽度小于高压晶体管的相对于第三侧壁绝缘膜的厚度。

3. 发明申请

US20120045875A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120045875A1
公开(公告)日：2012-02-23
申请号：US13111280
申请日：2011-05-19
申请人： Junichi Ariyoshi , Taiji Ema
发明人： Junichi Ariyoshi , Taiji Ema
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823857
摘要： A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.
摘要翻译：一种制造半导体器件的方法包括：分别在第一至第三区域中形成第一至第三栅电极; 在暴露所述第一和第三区域的同时形成覆盖所述第二区域的第一掩模图案; 通过使用第一掩模图案作为掩模通过离子注入形成p型源极漏极延伸和p型空穴区域; 通过使用第一掩模图案作为掩模的离子注入形成n型源极漏极延伸; 形成覆盖所述第一和第三区域同时暴露所述第二区域的第二掩模图案; 以及通过将第二掩模图案用作掩模将铟的离子注入到硅衬底中形成p型袋区域。

4. 发明申请

US20120034751A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120034751A1
公开(公告)日：2012-02-09
申请号：US13106129
申请日：2011-05-12
申请人： Junichi Ariyoshi , Taiji Ema , Toru Anezaki
发明人： Junichi Ariyoshi , Taiji Ema , Toru Anezaki
IPC分类号： H01L21/02
CPC分类号： H01L27/11526 , H01L21/823462 , H01L21/823857 , H01L27/0629 , H01L27/105 , H01L27/11546 , H01L28/60
摘要： A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.
摘要翻译：一种制造半导体器件的方法包括在第一区域形成闪存单元，在第二区域形成电容器的第一电极，形成第一氧化硅膜，氮化硅膜和第二氧化硅膜作为第二绝缘膜，在第一电极的部分区域中去除氮化硅膜和第二氧化硅膜，在第三区域中湿蚀刻第一绝缘膜和第二绝缘膜，形成第二绝缘膜的第二电极电容器，并且蚀刻并去除部分区域中的第一氧化硅膜。

5. 发明授权

US07723825B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07723825B2
公开(公告)日：2010-05-25
申请号：US11589084
申请日：2006-10-30
申请人： Taiji Ema , Masayoshi Asano , Toru Anezaki , Junichi Ariyoshi
发明人： Taiji Ema , Masayoshi Asano , Toru Anezaki , Junichi Ariyoshi
IPC分类号： H01L29/00
CPC分类号： H01L21/823892 , H01L27/0921 , H01L27/11803
摘要： According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.
摘要翻译：根据本发明，提供一种半导体器件，包括：p型硅衬底; 在硅衬底中形成浅的n阱; 在硅衬底中的浅n阱旁边形成浅的p阱; 以及在硅衬底中的浅p-阱旁边形成深深的n阱，并且比深p阱更深。此外，在浅层p阱和硅衬底中的深n阱之间形成深浅的p阱，其深于浅的p阱。

6. 发明授权

US08741727B2 Method of manufacturing semiconductor device capable of reducing a size of the semiconductor device 有权
标题翻译：能够减小半导体器件的尺寸的半导体器件的制造方法
公开(公告)号：US08741727B2
公开(公告)日：2014-06-03
申请号：US13106129
申请日：2011-05-12
申请人： Junichi Ariyoshi , Taiji Ema , Toru Anezaki
发明人： Junichi Ariyoshi , Taiji Ema , Toru Anezaki
IPC分类号： H01L21/02
CPC分类号： H01L27/11526 , H01L21/823462 , H01L21/823857 , H01L27/0629 , H01L27/105 , H01L27/11546 , H01L28/60
摘要： A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.
摘要翻译：一种制造半导体器件的方法包括在第一区域形成闪存单元，在第二区域形成电容器的第一电极，形成第一氧化硅膜，氮化硅膜和第二氧化硅膜作为第二绝缘膜，在第一电极的部分区域中去除氮化硅膜和第二氧化硅膜，在第三区域中湿蚀刻第一绝缘膜和第二绝缘膜，形成第二绝缘膜的第二电极电容器，并且蚀刻并去除部分区域中的第一氧化硅膜。

7. 发明授权

US08415215B2 Method of manufacturing semiconductor device with multiple implantation steps 有权
标题翻译：制造具有多个注入步骤的半导体器件的方法
公开(公告)号：US08415215B2
公开(公告)日：2013-04-09
申请号：US13111280
申请日：2011-05-19
申请人： Junichi Ariyoshi , Taiji Ema
发明人： Junichi Ariyoshi , Taiji Ema
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/8236 , H01L21/425
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823857
摘要： A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.
摘要翻译：一种制造半导体器件的方法包括：分别在第一至第三区域中形成第一至第三栅电极; 在暴露所述第一和第三区域的同时形成覆盖所述第二区域的第一掩模图案; 通过使用第一掩模图案作为掩模通过离子注入形成p型源极漏极延伸和p型空穴区域; 通过使用第一掩模图案作为掩模的离子注入形成n型源极漏极延伸; 形成覆盖所述第一和第三区域同时暴露所述第二区域的第二掩模图案; 以及通过将第二掩模图案用作掩模将铟的离子注入到硅衬底中形成p型袋区域。

8. 发明申请

US20080001258A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080001258A1
公开(公告)日：2008-01-03
申请号：US11589084
申请日：2006-10-30
申请人： Taiji Ema , Masayoshi Asano , Toru Anezaki , Junichi Ariyoshi
发明人： Taiji Ema , Masayoshi Asano , Toru Anezaki , Junichi Ariyoshi
IPC分类号： H01L29/00 , H01L31/0288 , H01L21/8234 , H01L21/336
CPC分类号： H01L21/823892 , H01L27/0921 , H01L27/11803
摘要： According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.
摘要翻译：根据本发明，提供一种半导体器件，包括：p型硅衬底; 在硅衬底中形成浅的n阱; 在硅衬底中的浅n阱旁边形成浅的p阱; 以及在硅衬底中的浅p-阱旁边形成深深的n阱，并且比深p阱更深。此外，在浅层p阱和硅衬底中的深n阱之间形成深浅的p阱，其深于浅的p阱。

9. 发明授权

US08247290B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08247290B2
公开(公告)日：2012-08-21
申请号：US12163168
申请日：2008-06-27
申请人： Junichi Ariyoshi , Toru Anezaki , Hiroshi Morioka
发明人： Junichi Ariyoshi , Toru Anezaki , Hiroshi Morioka
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11531
摘要： A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.
摘要翻译：一种制造半导体器件的方法，在半导体衬底上形成第一导电膜，蚀刻第一导电膜，形成沿第一方向布置的多个第一导电图案，并且在位于在所述多个第一导电图案中的一端，使得所述侧表面具有小于位于所述端部的所述导电图案的内侧上的侧表面的第二倾斜角的第一倾斜角度，在所述多个第一导电图案中形成第一绝缘膜的第一导电图案，并且在第一绝缘膜上形成第二导电图案。

10. 发明授权

US06830978B2 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US06830978B2
公开(公告)日：2004-12-14
申请号：US10643970
申请日：2003-08-20
申请人： Junichi Ariyoshi , Satoshi Torii
发明人： Junichi Ariyoshi , Satoshi Torii
IPC分类号： H01I21336
CPC分类号： H01L27/11526 , H01L21/76897 , H01L27/105 , H01L27/11546 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.
摘要翻译：在其上形成有栅电极和LDD层的半导体衬底上，形成作为硅化物块的SiN膜。为SiN膜提供与LDD层连通的开口。通过开口将杂质引入LDD层以形成源/漏层，并将其表面硅化以形成硅化物膜。接下来，形成SiO 2的层间绝缘膜，然后在SiO x的蚀刻速率高于SiN的蚀刻速率的条件下进行蚀刻，以形成从层间绝缘膜的上表面经由开口到达LDD层的接触孔。

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