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1. 发明专利

AT364885T 未知
公开(公告)号：AT364885T
公开(公告)日：2007-07-15
申请号：AT02254491
申请日：2002-06-26
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU , FONG YUPIN , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C11/56 , G11C16/00 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

2. 发明专利

DE60220590D1 未知
公开(公告)号：DE60220590D1
公开(公告)日：2007-07-26
申请号：DE60220590
申请日：2002-06-26
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU , FONG YUPIN , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C11/56 , G11C16/00 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

3. 发明专利

DE602004022353D1 未知
公开(公告)号：DE602004022353D1
公开(公告)日：2009-09-17
申请号：DE602004022353
申请日：2004-04-15
申请人： TOSHIBA KK , SANDISK CORP
发明人： TANAKA TOMOHARU , QUADER KHANDKER N , DOHMAE HIROYUKI , SATO TAKEAKI , INOUE ATSUSHI
IPC分类号： G06F12/16 , G11C16/26 , G06F3/06 , G06F3/08 , G06F12/00 , G06F12/06 , G06K17/00 , G06K19/07 , G11C7/10 , G11C16/06 , G11C16/10 , G11C16/32 , G11C17/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells (1a, 1b), an interface (6, 7, 9) making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit (2a, 2b, 3a, 3b, 4a, 4b, 5a, 5b) for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N + M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.

4. 发明专利

DE60220590T2 未知
公开(公告)号：DE60220590T2
公开(公告)日：2008-02-14
申请号：DE60220590
申请日：2002-06-26
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU , FONG YUPIN , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C11/56 , G11C16/00 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

5. 发明专利

AU6828701A Eeprom memory chip with multiple use pinouts 未知
公开(公告)号：AU6828701A
公开(公告)日：2001-12-17
申请号：AU6828701
申请日：2001-06-08
申请人： SANDISK CORP
发明人： CERNEA RAUL-ADRIAN , QUADER KHANDKER N , MEHROTRA SANJAY
IPC分类号： G11C16/06 , G11C5/06 , G11C16/30
摘要： The present invention reduces the demand on the number of pins of an EEPROM memory chip or flash EEPROM chip by multiplexing a subset of the pins between the high voltage generator circuit of the chip and the chip select circuit. When the chip receives an enable signal, the subset of pins are connected to the chip's charge pump circuit allowing it to be connected to an external set of capacitors through these pins. When the enable signal is de-asserted, the subset of pins are connected to the chip select circuit. When the chip is part of an array of chips, this allows this subset of pins to be used to assign a chip address for determining the chips position in the array. When a number of chips are placed in an array, one (or more) of the chips supplies the other chips in the array with the high voltage and current needed for erasing and programming. To be able to do this, this chip is enabled and connected through the subset of pins to the external capacitors. The other chips are not enabled and use the subset of pins to determine their array address. As the enabled chip (or chips) can not have its address specified in this way, it is placed in a predetermined location within the array and this predetermined address is supplied to the chip select circuit in response to the enable signal.

6. 发明专利

JP2006351192A METHOD OF REDUCING DISTURBS IN NON-VOLATILE MEMORY 审中-公开
公开(公告)号：JP2006351192A
公开(公告)日：2006-12-28
申请号：JP2006211081
申请日：2006-08-02
申请人： SANDISK CORP
发明人： MANGAN JOHN S , GUTERMAN DANIEL C , SAMACHISA GEORGE , MURPHY BRIAN , WANG CHI-MING , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/12
摘要： PROBLEM TO BE SOLVED: To provide a method of reducing disturbs in an electrically erasable and programmable read-only memory (EEPROM), regarding a non-volatile memory. SOLUTION: The non-volatile memory device comprises a plurality of word lines; a plurality of bit lines; a plurality of non-volatile memory cells connected to respective first bit lines and respective first word lines, in which a first voltage is applied to the respective first word lines to which predetermined cells are connected, and further a second voltage is applied to the respective first bit lines to which predetermined cells are connected, thereby storing information into a predetermined cell of the cells; and a bit line driver connected to one or more of the bit lines, in which a rate at which the bit driver changes a voltage applied to the bit lines connected to the driver is adjustable. COPYRIGHT: (C)2007,JPO&INPIT

7. 发明专利

AU2003230560A1 METHOD AND APPARATUS FOR IMPROVING THE READ ACCESS TIME IN A NON-VOLATILE MEMORY SYSTEM 未知
公开(公告)号：AU2003230560A1
公开(公告)日：2003-12-22
申请号：AU2003230560
申请日：2003-02-20
申请人： SANDISK CORP
发明人： PHAM LONG C , GROSS STEPHEN J , TUERS EDWARD P , QUADER KHANDKER N , MAK ALEXANDER K
IPC分类号： G11C7/10 , G11C16/26

8. 发明专利

AU2002251705A1 Method of reducing disturbs in non-volatile memory 未知
公开(公告)号：AU2002251705A1
公开(公告)日：2002-07-30
申请号：AU2002251705
申请日：2001-10-26
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , WANG CHI-MING , MURPHY BRIAN , MANGAN JOHN S , GUTERMAN DANIEL C , SAMACHISA GEORGE
IPC分类号： G11C16/02 , G11C16/12 , G11C16/34 , G11C16/10 , G11C16/32
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

9. 发明专利

JP2003109386A OPERATING TECHNIQUE FOR REDUCING EFFECT OF COUPLING BETWEEN STORAGE ELEMENTS OF NONVOLATILE MEMORY OPERATED IN MULTIPLE DATA STATES 审中-公开
公开(公告)号：JP2003109386A
公开(公告)日：2003-04-11
申请号：JP2002187020
申请日：2002-06-27
申请人： SANDISK CORP , TOSHIBA CORP
发明人： CHEN JIAN , TANAKA TOMOHARU , FONG YUPIN , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To minimize the effect of charge coupling between adjacent floating gates and to compress the distribution. SOLUTION: A flash electrically erasable and programmable ROM (EEPROM) in which storage elements are electrically floating gates is operated so that the effect of charge coupled between adjacent floating gates is minimized by programming again one part of cells after programming of adjacent cells. Also, second programming operation compacts the distribution for a charge level within at least some of the programming states. This increases the separation between states and allows more states to be included within a given storage window.

10. 发明专利

AT304748T 未知
公开(公告)号：AT304748T
公开(公告)日：2005-09-15
申请号：AT01948299
申请日：2001-06-08
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , HUYNH SHARON Y
IPC分类号： H03F3/343 , G11C7/02 , G11C11/56 , G11C27/00 , H03F3/00
摘要： A multiple output current mirror of improved accuracy suitable for use in a multi-level memory or analog applications is described. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror. By altering the physical arrangement of the pieces from one partial mirror to the next, variations in operating characteristics and manufacturing processes that are dependent upon positions are reduced since the variation in one partial mirror offsets that in another partial mirror. In an exemplary embodiment, the mirrored element, producing the reference current, and the mirroring elements in each of k branches are each composed of N transistors with a width w, giving an effective width W=Nw for each element and consequently a mirroring ration of 1 for all the branches. All of these N(k+1) transistors are physical placed in a linear arrangement of N partial current mirrors of (k+1) transistors each, where each partial mirror contains a transistor supplying part of the mirrored current and one transistor from each of the k branches mirroring it. Each of the N partial mirrors has its (k+1) elements arranged in a different permutation. The N=5, k=3 case is described in some detail.

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