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1. 发明专利

AU3840401A Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks 未知
公开(公告)号：AU3840401A
公开(公告)日：2001-08-27
申请号：AU3840401
申请日：2001-02-13
申请人： SANDISK CORP
发明人： CONLEY KEVIN M , MANGAN JOHN S , CRAIG JEFFREY G
IPC分类号： G06F3/06 , G06F12/00 , G06F12/02 , G11C20060101 , G11C11/34 , G11C16/04 , G11C16/08
摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

2. 发明专利

AU2002251705A1 Method of reducing disturbs in non-volatile memory 未知
公开(公告)号：AU2002251705A1
公开(公告)日：2002-07-30
申请号：AU2002251705
申请日：2001-10-26
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , WANG CHI-MING , MURPHY BRIAN , MANGAN JOHN S , GUTERMAN DANIEL C , SAMACHISA GEORGE
IPC分类号： G11C16/02 , G11C16/12 , G11C16/34 , G11C16/10 , G11C16/32
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

3. 发明专利

HK1058563A1 FLASH EEPROM SYSTEM WITH SIMULTANEOUS MULTIPLE DATA SECTOR PROGRAMMING AND STORAGE OF PHYSICAL BLOCK CHARACTERISTICS IN OTHER DESIGNATED BLOCKS 未知
公开(公告)号：HK1058563A1
公开(公告)日：2004-05-21
申请号：HK04101214
申请日：2004-02-20
申请人： SANDISK CORP
发明人： CONLEY KEVIN M , MANGAN JOHN S , CRAIG JEFFREY G
IPC分类号： G06F20090101 , G06F3/06 , G06F12/00 , G06F12/02 , G11C20060101 , G11C11/34 , G11C16/04 , G11C16/08
摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

4. 发明专利

JP2006351192A METHOD OF REDUCING DISTURBS IN NON-VOLATILE MEMORY 审中-公开
公开(公告)号：JP2006351192A
公开(公告)日：2006-12-28
申请号：JP2006211081
申请日：2006-08-02
申请人： SANDISK CORP
发明人： MANGAN JOHN S , GUTERMAN DANIEL C , SAMACHISA GEORGE , MURPHY BRIAN , WANG CHI-MING , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/12
摘要： PROBLEM TO BE SOLVED: To provide a method of reducing disturbs in an electrically erasable and programmable read-only memory (EEPROM), regarding a non-volatile memory. SOLUTION: The non-volatile memory device comprises a plurality of word lines; a plurality of bit lines; a plurality of non-volatile memory cells connected to respective first bit lines and respective first word lines, in which a first voltage is applied to the respective first word lines to which predetermined cells are connected, and further a second voltage is applied to the respective first bit lines to which predetermined cells are connected, thereby storing information into a predetermined cell of the cells; and a bit line driver connected to one or more of the bit lines, in which a rate at which the bit driver changes a voltage applied to the bit lines connected to the driver is adjustable. COPYRIGHT: (C)2007,JPO&INPIT

5. 发明申请

WO0161703A3 FLASH EEPROM SYSTEM WITH SIMULTANEOUS MULTIPLE DATA SECTOR PROGRAMMING AND STORAGE OF PHYSICAL BLOCK CHARACTERISTICS IN OTHER DESIGNATED BLOCKS 审中-公开
标题翻译：具有同时多个数据部分的闪存EEPROM系统编程和存储其他指定块中的物理块特性
公开(公告)号：WO0161703A3
公开(公告)日：2002-07-18
申请号：PCT/US0105052
申请日：2001-02-13
申请人： SANDISK CORP
发明人： CONLEY KEVIN M , MANGAN JOHN S , CRAIG JEFFREY G
IPC分类号： G06F3/06 , G06F12/00 , G06F12/02 , G11C20060101 , G11C11/34 , G11C16/04 , G11C16/08
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7203 , G06F2212/7207 , G06F2212/7208 , G11C16/10 , G11C16/3459 , G11C29/82 , G11C2216/14
摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.
摘要翻译：非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。该系统包括可以单独地或以各种协作组合实现的多个特征。一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围，使得容易制造具有不同容量的存储器芯片的存储器系统。存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

6. 发明申请

WO02058073A2 METHOD OF REDUCING DISTURBS IN NON-VOLATILE MEMORY 审中-公开
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：WO02058073A2
公开(公告)日：2002-07-25
申请号：PCT/US0150168
申请日：2001-10-26
申请人： SANDISK CORP
发明人： MANGAN JOHN S , GUTERMAN DANIEL C , SAMACHISA GEORGE , MURPHY BRIAN , WANG CHI-MING , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/12 , G11C16/00
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in distrubs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selected the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drives change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，当阵列位线上的电压电平发生变化时，在未选择的字线中产生的位移电流可导致分配。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这通过选择要并行编程的单元数量和它们的顺序来完成，使得所有编程在一起的单元都是来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

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