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1. 发明申请

WO2005029504A2 METHODS FOR IDENTIFYING NON-VOLATILE MEMORY ELEMENTS WITH POOR SUBTHRESHOLD SLOPE OR WEAK TRANSCONDUCTANCE 审中-公开
标题翻译：用于识别具有较差的基底坡度或弱交叉缺陷的非易失性记忆元素的方法
公开(公告)号：WO2005029504A2
公开(公告)日：2005-03-31
申请号：PCT/US2004030493
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK , LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/02 , G11C16/04 , G11C16/34 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C29/00
CPC分类号： G11C16/3495 , G11C16/04 , G11C16/349 , G11C29/50 , G11C29/50004
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.
摘要翻译：本发明提出了用于鉴定具有差的亚阈值斜率和降低的跨导的细胞的多种方法。第一组技术集中在通过循环单元的劣化存储元件的差的亚阈值行为，然后将它们编程到高于基态的状态并且以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然进行。第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线是相对稳定的，而退化元件表现出较大的偏移。偏移量可以用来区分好的元素和坏的元素。

2. 发明专利

DE602004031139D1 PROGRAMMIERUNGSVERFAHREN AUF DER BASIS DES VERHALTENS NICHTFLÜCHTIGER SPEICHERZELLEN 未知
公开(公告)号：DE602004031139D1
公开(公告)日：2011-03-03
申请号：DE602004031139
申请日：2004-10-12
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , LUTZE JEFFREY W , LI YAN , GUTERMAN DANIEL C , TOMOHARU TANAKA
IPC分类号： G11C11/56 , G11C16/04 , G11C16/02 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792

3. 发明专利

DE60220590T2 未知
公开(公告)号：DE60220590T2
公开(公告)日：2008-02-14
申请号：DE60220590
申请日：2002-06-26
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU , FONG YUPIN , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C11/56 , G11C16/00 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

4. 发明专利

DE602004013347D1 未知
公开(公告)号：DE602004013347D1
公开(公告)日：2008-06-05
申请号：DE602004013347
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/34 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

5. 发明专利

AT393453T 未知
公开(公告)号：AT393453T
公开(公告)日：2008-05-15
申请号：AT04784376
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/34 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

6. 发明专利

AT533161T 未知
公开(公告)号：AT533161T
公开(公告)日：2011-11-15
申请号：AT08004345
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/34 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

7. 发明专利

AT496373T 未知
公开(公告)号：AT496373T
公开(公告)日：2011-02-15
申请号：AT04795181
申请日：2004-10-12
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , LUTZE JEFFREY , LI YAN , GUTERMAN DANIEL , TOMOHARU TANAKA
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

8. 发明专利

DE60319437T2 未知
公开(公告)号：DE60319437T2
公开(公告)日：2009-02-19
申请号：DE60319437
申请日：2003-12-18
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU
IPC分类号： G11C16/34 , G06F12/00 , G11C11/24 , G11C11/34 , G11C11/56 , G11C16/04 , H01L27/115
摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.

9. 发明专利

AT387715T 未知
公开(公告)号：AT387715T
公开(公告)日：2008-03-15
申请号：AT03815779
申请日：2003-12-18
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU
IPC分类号： G11C16/34 , G06F12/00 , G11C11/24 , G11C11/34 , G11C11/56 , G11C16/04 , H01L27/115
摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.

10. 发明专利

DE60220590D1 未知
公开(公告)号：DE60220590D1
公开(公告)日：2007-07-26
申请号：DE60220590
申请日：2002-06-26
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU , FONG YUPIN , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C11/56 , G11C16/00 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

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