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1. 发明申请

WO2005029504A2 METHODS FOR IDENTIFYING NON-VOLATILE MEMORY ELEMENTS WITH POOR SUBTHRESHOLD SLOPE OR WEAK TRANSCONDUCTANCE 审中-公开
标题翻译：用于识别具有较差的基底坡度或弱交叉缺陷的非易失性记忆元素的方法
公开(公告)号：WO2005029504A2
公开(公告)日：2005-03-31
申请号：PCT/US2004030493
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK , LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/02 , G11C16/04 , G11C16/34 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C29/00
CPC分类号： G11C16/3495 , G11C16/04 , G11C16/349 , G11C29/50 , G11C29/50004
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.
摘要翻译：本发明提出了用于鉴定具有差的亚阈值斜率和降低的跨导的细胞的多种方法。第一组技术集中在通过循环单元的劣化存储元件的差的亚阈值行为，然后将它们编程到高于基态的状态并且以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然进行。第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线是相对稳定的，而退化元件表现出较大的偏移。偏移量可以用来区分好的元素和坏的元素。

2. 发明授权

US6363010B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6363010B2
公开(公告)日：2002-03-26
申请号：US89929001
申请日：2001-07-06
申请人： TOSHIBA KK
发明人： TANAKA TOMOHARU , OHUCHI KAZUNORI , TANZAWA TORU , TAKEUCHI KEN
IPC分类号： G11C7/10 , G11C7/12 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/3459 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.
摘要翻译：提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

3. 发明授权

US6434055B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6434055B2
公开(公告)日：2002-08-13
申请号：US76715201
申请日：2001-01-23
申请人： TOSHIBA KK
发明人： TANAKA TOMOHARU , NAKAMURA HIROSHI , TAKEUCHI KEN , SHIROTA RIICHIRO , ARAI FUMITAKA , FUJIMURA SUSUMU
IPC分类号： G11C7/00 , G11C11/56 , G11C16/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译：包括串联连接的多个存储单元的NAND单元单元。对所有存储单元进行擦除操作。然后，对所有存储单元施加与施加在擦除操作中的擦除电压极性相反的软编程电压，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到任何一个存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并将11V施加到控制栅极的剩余存储单元。因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

4. 发明专利

DE602004022353D1 未知
公开(公告)号：DE602004022353D1
公开(公告)日：2009-09-17
申请号：DE602004022353
申请日：2004-04-15
申请人： TOSHIBA KK , SANDISK CORP
发明人： TANAKA TOMOHARU , QUADER KHANDKER N , DOHMAE HIROYUKI , SATO TAKEAKI , INOUE ATSUSHI
IPC分类号： G06F12/16 , G11C16/26 , G06F3/06 , G06F3/08 , G06F12/00 , G06F12/06 , G06K17/00 , G06K19/07 , G11C7/10 , G11C16/06 , G11C16/10 , G11C16/32 , G11C17/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells (1a, 1b), an interface (6, 7, 9) making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit (2a, 2b, 3a, 3b, 4a, 4b, 5a, 5b) for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N + M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.

5. 发明专利

DE60220590T2 未知
公开(公告)号：DE60220590T2
公开(公告)日：2008-02-14
申请号：DE60220590
申请日：2002-06-26
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU , FONG YUPIN , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/04 , G11C11/56 , G11C16/00 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

6. 发明专利

DE602004013347D1 未知
公开(公告)号：DE602004013347D1
公开(公告)日：2008-06-05
申请号：DE602004013347
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/34 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

7. 发明专利

AT393453T 未知
公开(公告)号：AT393453T
公开(公告)日：2008-05-15
申请号：AT04784376
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/34 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

8. 发明专利

AT533161T 未知
公开(公告)号：AT533161T
公开(公告)日：2011-11-15
申请号：AT08004345
申请日：2004-09-16
申请人： SANDISK CORP , TOSHIBA KK
发明人： LUTZE JEFFREY , CHEN JIAN , LI YAN , KANEBAKO KAZUNORI , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/34 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

9. 发明专利

DE60319437T2 未知
公开(公告)号：DE60319437T2
公开(公告)日：2009-02-19
申请号：DE60319437
申请日：2003-12-18
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , TANAKA TOMOHARU
IPC分类号： G11C16/34 , G06F12/00 , G11C11/24 , G11C11/34 , G11C11/56 , G11C16/04 , H01L27/115
摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.

10. 发明专利

DE69738992D1 未知
公开(公告)号：DE69738992D1
公开(公告)日：2008-10-23
申请号：DE69738992
申请日：1997-03-18
申请人： TOSHIBA KK
发明人： TAKEUCHI KEN , TANAKA TOMOHARU
IPC分类号： G11C11/56
摘要： A multilevel semiconductor EEPROM device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), €ƒ€ƒ€ƒ wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level, and during the kth programming operation, each memory cell stores "A" in the input data is a (2k-1)th logic level and stores "A+2 k-1 " in the input data is a 2kth logic level in the case where the memory cell has been storing "A" during a (k-1)th programming operation (k is 2 or a greater natural number).

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