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1. 发明专利

JPS61172374A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS61172374A
公开(公告)日：1986-08-04
申请号：JP1375685
申请日：1985-01-28
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PURPOSE:To rewrite and read data at high speed by using a transistor with a floating gate and to control gates as memory cells. CONSTITUTION:Arsenic ion are implanted to the surface of a p-type silicon semiconductor substrate 31 to form an n type semiconductor region 32. A polycrystalline silicon layer 36 is deposited and shaped onto the whole surface through a vapor growth method, and a floating gate 36A is formed through patterning. Likewise, a first control gate 39 and a second control gate 42A are shaped. In a memory device consisting of such constitution, source regions in memory cells are isolated at every two cell, n type semiconductor regions 47 are connected by wirings 49 composed of aluminum having high conductivity, and areas are reduced. Accordingly, diffusion resistance, diffusion capacitance, junction capacitance generated between the memory device and the substrate and the values of leakage currents are minimized extremely.

2. 发明专利

JPS6318592A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS6318592A
公开(公告)日：1988-01-26
申请号：JP15974486
申请日：1986-07-09
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD , TOSHIBA MICRO CUMPUTER ENG
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO , KUMAGAI SHIGERU , SATO ISAO
IPC分类号： H01L21/8247 , G11C17/00 , H01L21/822 , H01L27/04 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To eliminate a drop in the drain voltage of a memory cell at the time of writing data, to make strong to the unevenness in a process and to write the data at high speed by using a booster circuit as a power switching circuit and applying this voltage to the buffer of a decoder. CONSTITUTION:At the time of an ordinary reading, the same voltage as VCC is impressed to the voltage of a source VPP, signals -W, HD, -HD are respectively logics '1', '0', '1', a transistor T37 is turned on and the output of a node SW1 has the same voltage as the VCC. On the other hand, at the time of writing the data, a higher voltage than the power source VCC is impressed to the power source VPP. The signals -W, HD, -HD go to the logics '0', '1', '0'. Accordingly, a signal from a ring oscillator constituted of inverters I2-I6 is applied to an inverter consisting of transistors T23-T25 and the buffer consisting of transistors T26-T28 through an inverter I7, the potential of the node SW1 is raised for every clock pulse and finally, stable at a voltage higher by the threshold voltage of the transistor T36 than the power source VPP.

3. 发明专利

DE3481668D1 未知
公开(公告)号：DE3481668D1
公开(公告)日：1990-04-19
申请号：DE3481668
申请日：1984-08-21
申请人： TOSHIBA KAWASAKI KK , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： IWAHASHI HIROSHI C O PATENT DI , ASANO MASAMICHI C O PATENT DIV , MOMODOMI MASAKI C O PATENT DIV , MINAGAWA HIDENOBU , SUZUKI KAZUTO , NARITA AKIRA
IPC分类号： G11C16/12 , G11C16/30 , G11C17/00

4. 发明专利

JPS6314400A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS6314400A
公开(公告)日：1988-01-21
申请号：JP15729986
申请日：1986-07-04
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD , TOSHIBA MICRO CUMPUTER ENG
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO , KUMAGAI SHIGERU , SATO ISAO
IPC分类号： G11C29/00 , G11C17/00 , G11C29/12
摘要： PURPOSE:To attain the measurement of an electric characteristic even if the titled memory is sealed into a package by setting all row lines into the non- selecting state before data is read from a memory cell in the erasure state even if all memory cells are erased in advance to apply the similar operation to data read. CONSTITUTION:In setting a voltage V31 at a terminal 31 to a high level to bring all row lines 11 into non-selecting state, and after storage data of the memory cell in the write state substantially are read, an external address signal is fed to the terminal 31 in place of a high voltage. Then one row line corresponding to the address is driven selectively to read the storage data in the memory cell in the erasure state. Thus, data write is executed only once and even with no data erasure, the manufacture cost is made inexpensive and even if the element is sealed in the package, the electric characteristic is measured.

5. 发明专利

JPS6318595A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6318595A
公开(公告)日：1988-01-26
申请号：JP15974386
申请日：1986-07-09
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , KUMAGAI SHIGERU , SATO ISAO , SUZUKI KAZUTO
IPC分类号： H01L27/10 , G11C17/00
摘要： PURPOSE:To correct the fluctuation in the quantity of discharged current of a discharging transistor due to the fluctuation in a process by changing the number of a first resistance elements or a second resistance elements and controlling the gate of a third transistor by a voltage obtained by dividing a power source voltage by a resistance. CONSTITUTION:There are provided the plural first resistance elements F, H, J, L connected in parallel to a first power source Vcc, the second resistance elements G, I, K, M connected in series and respectively correspondingly to the first resistance elements F, H, J, L and connected to a second power source VSS and a third transistor T3 having a gate connected to the respective connecting points of the second resistance elements G, I, K, M and the first resistance elements F, H, J, L and the number of the first resistance elements F, H, J, L or the second resistance elements G, I, K, M is changed, thereby, the quantity of current conducting through the third transistor T3 is changed. Thereby, after an IC is formed, the value of leaked current can be freely adjusted by a laser cutting or the like and a stable reading speed can be obtained.

6. 发明专利

JPS6316716A BOOSTING CIRCUIT 失效
公开(公告)号：JPS6316716A
公开(公告)日：1988-01-23
申请号：JP15974286
申请日：1986-07-09
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , SATO ISAO , KUMAGAI SHIGERU , SUZUKI KAZUTO
IPC分类号： H03K19/003 , G11C11/34 , G11C11/407 , G11C16/06 , H01L27/10 , H02M3/07 , H03K17/06 , H03K17/16 , H03K19/094 , H03K19/0952 , H03K19/096
摘要： PURPOSE:To eliminate the adverse effect onto a peripheral circuit comprising CMOS transistors (TRs) by eliminating a pulse waveform from a boosted output voltage. CONSTITUTION:In using a TR TA as a capacitor, the potential change of a pulse fed to a gate of a TR T3 slows down and it slows down the potential change in a pulse flowing from a drain of the TR T3 to the source thereby slowing down the potential change at a node B. Thus, the potential change of the node A is transferred to a node A by the capacitive coupling between the nodes B and A, the potential of the node A rises, and in giving the increase to a node OUT via a TR T7 of diode connection, the potential change of the node B slows down. Thus, the potential at the node OUT is not boosted more than the sum of the 3rd power voltage (Vpp) and the threshold voltage of TRs 9-11, and no pulse waveform appears at the output voltage of the node OUT.

7. 发明专利

JPS61172375A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS61172375A
公开(公告)日：1986-08-04
申请号：JP1375785
申请日：1985-01-28
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PURPOSE:To rewrite and read data at high speed by using a transistor with a floating gate and two control gates as memory cells. CONSTITUTION:A polycrystalline silicon layer 36 is deposited and formed through a vapor growth method, and a floating gate 36A positioned onto a tunnel insulating film 34 is shaped through patterning. Likewise, a polycrystalline silicon layer 39 is patterned to form a control gate 39A. A polycrystalline silicon layer 42 is patterned to shape a control gate 42A. The ions of phosphorus or arsenic are implanted into the surface of a substrate 31, thus forming a drain region 44 and a source region 45 consisting of n type semiconductor regions. In a memory cell array composed of such constitution, the values of diffusion resistance, diffusion capacitance, junction capacitance generated between a memory device and the substrate, and leakage currents, etc. are reduced extremely.

8. 发明专利

JPS59154692A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：JPS59154692A
公开(公告)日：1984-09-03
申请号：JP2877283
申请日：1983-02-23
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： G11C11/41 , G11C11/34 , G11C16/06 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To speed up data read speed by providing an MOS transister (TR) for discharging which discharges the charge on a data line coupled with plural memory cells so as to turn on an MOS TR7 when an address signal changes. CONSTITUTION:An MOS TR(Q)41 is connected between a circuit point S being an input terminal of a sense amplifier 36 and a reference potential point and an output signal from an NOR circuit 49 is inputted to its gate. Further, the output pulse from a pulse generating circuit 45 is inputted to the gate of a Q47 being a driving transistor to the NOR circuit 49 and the output signal from an inverter 44 is inputted to the gate of a Q48 being other driving TR respectively. Further, a signal at a connecting point between the Q46 and Q47, 48 in the NOR circuit 49 is inputted to the gate of the Q41 for discharge as an output signal in this circuit. A threshould voltage of said inverter 44 and a data sense level of the sense amplifier 36 are almost coincident with each other, then the discharge by the Q41 is attained in the vicinity of the sense level of the sense amplifier 36, thereby attaining the detection of data of the sense amplifier 36 in a short time.
摘要翻译：目的：通过提供放电的MOS转移器（TR）来加速数据读取速度，其中，在与多个存储单元耦合的数据线上放电，以便在地址信号改变时接通MOS TR7。构成：将MOS TR（Q）41连接在作为读出放大器36的输入端的电路点S与基准电位点之间，将来自NOR电路49的输出信号输入到其门。此外，来自脉冲发生电路45的输出脉冲被输入到NOR电路49的驱动晶体管的Q47的栅极，并且来自反相器44的输出信号分别输入到作为其他驱动TR的Q48的栅极。此外，在NOR电路49中的Q46与Q47,48之间的连接点处的信号作为该电路中的输出信号输入到用于放电的Q41的栅极。所述反相器44的检测电压和读出放大器36的数据感测电平几乎一致，则在读出放大器36的感测电平附近获得Q41的放电，从而实现检测在短时间内读出放大器36的数据。

9. 发明专利

JPH0668689A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0668689A
公开(公告)日：1994-03-11
申请号：JP24497492
申请日：1992-09-14
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSHIBA JOHO SYST KK
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , MOMOTOMI MASAKI , MINAGAWA EISHIN , SUZUKI KAZUTO , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent stationary flowing of current from a power supply by suppressing a MOSFET of P channel with a second MOSFET of depression type of N channel and turning off the second MOSFET when an signal at an output terminal is made 0 level. CONSTITUTION:When an input signal IN is made 0 level, voltage close to high voltage V is obtained as an output signal OUT, and data is written. In this case, current outflow from a circuit point 27 to which VH is impressed is only a current for charging a circuit point 30, and stationary current outflow does not occur. Further, when the input signal is made 1 level, earth voltage VS, that is, voltage of 0V is obtained as the output signal OUT. In a memory cell in which this voltage is impressed to a control gate, threshold value voltage is not varied. In this case, current outflow from the circuit point 27 is only a leak current.

10. 发明专利

JPS59165522A Output buffer circuit 失效
标题翻译：输出缓冲电路
公开(公告)号：JPS59165522A
公开(公告)日：1984-09-18
申请号：JP3861283
申请日：1983-03-09
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/0944
CPC分类号： H03K5/023
摘要： PURPOSE:To have an output buffer circuit with which an integration circuit having a wide working margin is obtained by setting the DC current flowing between power supplies at zero via each output buffer transistor. CONSTITUTION:The gate of a driver transistor TR7 is connected to a point B which serves as a gate driving source of a TR12. A node A is set at level ''1'' after the node B is set at level ''0'' and the TR7 and 12 are turned off since the TR7 is driven by the output of the driving circuit of the TR12. Then a TR11 is turned on, and therefore the current which flows between power supplies VC and VS via TR11 and 12 is not produced when the data D is changed to ''1'' from ''0''.
摘要翻译：目的：通过将通过每个输出缓冲晶体管的电源之间流过的直流电流设置为零，获得具有宽工作余量的积分电路的输出缓冲电路。构成：驱动晶体管TR7的栅极连接到作为TR12的栅极驱动源的点B。在节点B设置在电平“0”之后，将节点A设置为电平“1”，并且由于TR7由TR12的驱动电路的输出驱动，TR7和12被截止。然后，TR11导通，因此当数据D从“0”变为“1”时，不产生通过TR11和12在电源VC和VS之间流动的电流。

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