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1. 发明专利

JPH05325581A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH05325581A
公开(公告)日：1993-12-10
申请号：JP24497392
申请日：1992-09-14
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSHIBA JOHO SYST KK
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , MOMOTOMI MASAKI , MINAGAWA EISHIN , SUZUKI KAZUTO , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07
摘要： PURPOSE:To prevent a current from flowing out steady from a high voltage when the high voltage is controlled inside by connecting a depletion type NMOSFET to a PMOSFET which forms an inverter. CONSTITUTION:The depletion type NMOSFET 29 which has its gate connected to a circuit point 30 and its drain connected to a circuit point 31 at a source voltage supply terminal is connected to the PMOSFET 21 forming the inverter 26 which inverts an input IN and sends out an output OUT. When the input IN becomes 0, an FET 21 turns ON to charge the circuit point 30 by the high voltage power source VH at a circuit point 27 and when the charging voltage reaches a specific value, FETs 29 and 31 turn OFF to only charge the circuit point 30 by the power source VH, thereby obtaining the semiconductor integrated circuit which prevents the steady current from flowing out of the power source VH.

2. 发明专利

JPH0668689A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0668689A
公开(公告)日：1994-03-11
申请号：JP24497492
申请日：1992-09-14
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSHIBA JOHO SYST KK
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , MOMOTOMI MASAKI , MINAGAWA EISHIN , SUZUKI KAZUTO , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent stationary flowing of current from a power supply by suppressing a MOSFET of P channel with a second MOSFET of depression type of N channel and turning off the second MOSFET when an signal at an output terminal is made 0 level. CONSTITUTION:When an input signal IN is made 0 level, voltage close to high voltage V is obtained as an output signal OUT, and data is written. In this case, current outflow from a circuit point 27 to which VH is impressed is only a current for charging a circuit point 30, and stationary current outflow does not occur. Further, when the input signal is made 1 level, earth voltage VS, that is, voltage of 0V is obtained as the output signal OUT. In a memory cell in which this voltage is impressed to a control gate, threshold value voltage is not varied. In this case, current outflow from the circuit point 27 is only a leak current.

3. 发明专利

JP2001266583A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001266583A
公开(公告)日：2001-09-28
申请号：JP2001029460
申请日：2001-02-06
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/12 , G11C29/44 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To shorten the time required for program-verification and erase- verification and to prevent over-variation of threshold voltage even if rewrite and reerase are performed. SOLUTION: This device is provided with a memory cell array which is arranged in a matrix state and in which memory cells having electric charges accumulating layers forms a matrix, a plurality of word lines connected commonly to the memory cells forming respective rows, a plurality of bit lines connected commonly to the memory cells forming respective columns, a means for selecting a word line and applying write voltage, and a plurality of data storage circuits which store control data of a first logic level or a second logic level deciding whether write control voltage for accumulating electric charges in the electric charge accumulating layers of the memory cells connected to the selected word line is to be applied to the bit line and which is arranged in respective bit lines. The control data of the second logic level deciding that the write control voltage is not applied to the bit line is stored in a data storage circuit other than the data storage circuit in which externally inputted control data are stored.

4. 发明专利

JP2001266582A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001266582A
公开(公告)日：2001-09-28
申请号：JP2001029361
申请日：2001-02-06
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/12 , G11C29/44 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To shorten the time required for program-verification and erase- verification and to prevent over-variation of threshold voltage even if rewrite and reerase are performed. SOLUTION: This device is provided with a memory cell array constituted of a plurality of non-volatile memory cells, a plurality of bit lines and a plurality of word lines, a plurality of data storage circuits storing control data of a first logic level or a second logic level deciding whether write voltage is to be applied to each of the plurality of selected memory cells, a write means in which the write voltage is applied to only memory cells corresponding to a data storage circuit in which control data are stored of the first logic level out of the plurality of selected memory cells on the basis of control data stored in the plurality of data storage circuits, and the write state of the memory cell is detected, control data of the plurality of data storage circuits are partly changed so that the write voltage is applied to only a memory cell detected as that it does not reach the prescribed write state, and a means for outputting the control data of the plurality of data storage circuit to the outside.

5. 发明专利

JPH07130888A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH07130888A
公开(公告)日：1995-05-19
申请号：JP18884393
申请日：1993-06-30
申请人： TOSHIBA CORP
发明人： NAKAMURA HIROSHI , TANAKA YOSHIYUKI , TANAKA TOMOHARU , MOMOTOMI MASAKI , OHIRA HIDEKO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C17/12 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a NAND cell type EEPROM which enables reduction of a required time for write operation without increasing a pattern area. CONSTITUTION:In a nonvolatile semiconductor memory device wherein a floating gate and a control gate are laminated on a channel region and a plurality of memory cells for carrying out data write and erasing by transferring of charge between a floating gate and a substrate are arranged, a NAND cell is constituted by connecting a plurality of memory cells in series and a block is constituted by connecting a plurality of the NAND cells. A memory cell is provided to a p-type well formed in an n-type substrate, and electric potential whose polarity is reverse to a positive potential applied to a control gate CG inside a selective block 202 is applied to the control gate CG inside non-selective blocks 201, 203 to 20n together with a p-type well during data write operation for selectively applying positive potential to the control gate CG inside the selective block 202.

6. 发明专利

JPH0786440A NONVOLATILE STORAGE DEVICE 失效
公开(公告)号：JPH0786440A
公开(公告)日：1995-03-31
申请号：JP22864593
申请日：1993-09-14
申请人： TOSHIBA CORP
发明人： MATSUZAWA KAZUYA , MOMOTOMI MASAKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To increase effective device width and obtain a large current value, by forming a gate electrode so as to fill the inside of a charge storage layer in the trench of a substrate. CONSTITUTION:A trench is formed in a semiconductor device. A titanium silicide film 6 is formed on the inner surface of the trench. N type polycrystalline silicon 7 is buried in the trench. A gate region is formed by eliminating the central part. A gate oxide film 8 and titanium oxide 9 are formed on the inner surface of the N type polycrystalline silicon 7 of the gate region. A control electrode is formed by burying N type polycrystalline silicon in the inside. A source.drain diffusion layer is formed by solid-phase diffusion from the N type polycrystalline silicon. A channel region between diffusion layers is formed on the side surface and the bottom surface in the gate region, so that the channel region has a large area as compared with the conventional one. Hence the effective device width is increased and a large current value can be obtained when the device size is reduced.

7. 发明专利

JPH05182474A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH05182474A
公开(公告)日：1993-07-23
申请号：JP5373292
申请日：1992-03-12
申请人： TOSHIBA CORP
发明人： ENDO TETSUO , SHIRATA RIICHIRO , OUCHI KAZUNORI , TANAKA YOSHIYUKI , KIRISAWA RYOHEI , ARITOME SEIICHI , TANAKA TOMOHARU , MOMOTOMI MASAKI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE:To set the threshold value of a memory cell in an optimum state by confirming a writing lack state with first write verifying potential and confirming a writing excess state with second write verifying potential. CONSTITUTION:The writing lack state is checked by applying a first write verifying potential VVER(1) to a word line and applying a Vcc to a nonselective word line in a NAND cell and reading them after data is written in all memory cells connected to the selected word line. When writing lack is present, the memory cell is written and checked again. Thereafter, the writing excess state is checked by applying the second write verifying potential VVER(2) to the selective word line and applying the Vcc to the nonselective word line in the NAND cell and reading them. In such a manner, the threshold value of the memory cell is set in the optimum state and reliability is improved by controlling the write verifying checking the upper limit and the lower limit of an allowable threshold value.

8. 发明专利

JPH0528780A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0528780A
公开(公告)日：1993-02-05
申请号：JP18126791
申请日：1991-07-22
申请人： TOSHIBA CORP
发明人： SAKUI YASUSHI , TANAKA TOMOHARU , IWATA YOSHIHISA , MOMOTOMI MASAKI , MASUOKA FUJIO
IPC分类号： G11C17/00 , G11C11/401 , G11C11/409 , G11C16/02 , G11C16/06
摘要： PURPOSE:To provide a nonvolatile semiconductor memory enabling of smooth high-speed reading by negligibly shortening the dead time occurring at a switching time of the word line. CONSTITUTION:Column reading for the data of a memory cell selected with one word line WL stored in a sense amplifier circuit 3 having a latching function provided with each bit line BLj is carried out. During this time, between the bit line BLj and the sense amplifier circuit 3 is cut-off by a bit line transfer gate Qj2 and a timing control is carried out such that reading of the bit line BLj of the data of the memory cell selected by the next word line WL is simultaneously carried out.

9. 发明专利

JPH04302477A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04302477A
公开(公告)日：1992-10-26
申请号：JP6722691
申请日：1991-03-29
申请人： TOSHIBA CORP
发明人： MATSUZAWA KAZUYA , MOMOTOMI MASAKI , FUKUDA SANAE , NAKAMURA MITSUTOSHI
IPC分类号： H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To increase the packing density of a semiconductor memory that includes cells capable of storing information at more than two different levels as opposed to the binary cell. CONSTITUTION:A columnar semiconductor layer 12 of a first conductivity type is vertically sandwiched between diffused layers 11 and 13 of a second conductive type. On both sides of the semiconductor layer 12 as a channel region, there are provided first insulating films 14 and 15, charge storage layers 16 and 17, second insulating films 18 and 19, and control gates 20 and 21.

10. 发明专利

JPH03295097A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH03295097A
公开(公告)日：1991-12-26
申请号：JP9504990
申请日：1990-04-12
申请人： TOSHIBA CORP
发明人： ARITOME SEIICHI , SHIRATA RIICHIRO , MOMOTOMI MASAKI , IWATA YOSHIHISA , KIRISAWA RYOHEI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent destruction of insulation film of a selection gate transistor (TR) at repetitive erasure by applying a prescribed potential to a gate of the selection gate TR at the erasure in an EEPROM employing a memory TR having a floating gate and a control gate. CONSTITUTION:A NAND cell type EEPROM is formed with control gate TRs QS1, QS2) and memory TRs M1 - M4 each having a floating gate and a control gate provided on a substrate in series connection. Then in the case of erasure, control gates CG1 - CG4 of the TRs M1 - M4 are brought into 0V, and a high level such as 18V is applied to the substrate to apply 18V to also selection gate lines SG1 - SG2, then electrons of the floating gate of the TRs M1 - M4 are discharged to a P-channel well and a threshold level is moved in the negative direction to apply erasure. Even when the erasure is repeated in the method in which a similar high level to a level fed to the substrate is applied to the gate of the selection gate TR, the destruction of the insulation film of the control gate TR is prevented and the reliability of the EEPROM is enhanced.

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