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1. 发明专利

JPS59165522A Output buffer circuit 失效
标题翻译：输出缓冲电路
公开(公告)号：JPS59165522A
公开(公告)日：1984-09-18
申请号：JP3861283
申请日：1983-03-09
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/0944
CPC分类号： H03K5/023
摘要： PURPOSE:To have an output buffer circuit with which an integration circuit having a wide working margin is obtained by setting the DC current flowing between power supplies at zero via each output buffer transistor. CONSTITUTION:The gate of a driver transistor TR7 is connected to a point B which serves as a gate driving source of a TR12. A node A is set at level ''1'' after the node B is set at level ''0'' and the TR7 and 12 are turned off since the TR7 is driven by the output of the driving circuit of the TR12. Then a TR11 is turned on, and therefore the current which flows between power supplies VC and VS via TR11 and 12 is not produced when the data D is changed to ''1'' from ''0''.
摘要翻译：目的：通过将通过每个输出缓冲晶体管的电源之间流过的直流电流设置为零，获得具有宽工作余量的积分电路的输出缓冲电路。构成：驱动晶体管TR7的栅极连接到作为TR12的栅极驱动源的点B。在节点B设置在电平“0”之后，将节点A设置为电平“1”，并且由于TR7由TR12的驱动电路的输出驱动，TR7和12被截止。然后，TR11导通，因此当数据D从“0”变为“1”时，不产生通过TR11和12在电源VC和VS之间流动的电流。

2. 发明专利

JPS59113591A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：JPS59113591A
公开(公告)日：1984-06-30
申请号：JP22465582
申请日：1982-12-21
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： G11C11/41 , G11C11/34 , G11C11/409 , G11C11/417
CPC分类号： G11C11/34
摘要： PURPOSE:To reduce the short-circuit current in an output buffer to stabilize the operation, by providing two buffer amplifying parts and controlling the operation of one buffer amplifying part in accordance with an output enable signal and grasping the change of an address signal to generate its delay signal. CONSTITUTION:Two buffer amplifying parts 10A and 10B are provided, and respective input terminals and output terminals are connected commonly. A control signal A is supplied to gates of MOSFETs 13A and 17A, and a control signal A' is supplied to gates of MOSFETs 16A and 20A respectively. A control signal B is supplied to gates of MOSFETs 13B and 17B, and a control signal B' is supplied to gates of MOSFETs 16B and 20B respectively. In case that an output buffer 5 and a CPU generates a short-circuit through a bus line, the time when a conventional excessive short-circuit current is flowed is very shorter because the buffer amplifying part 10B controlled by control signals B and B' is operated only for a prescribed time after the change of the address signal.
摘要翻译：目的：为了降低输出缓冲器中的短路电流以稳定运行，通过提供两个缓冲放大部分，并根据输出使能信号控制一个缓冲放大部分的工作，并掌握地址信号的变化以产生其延迟信号。构成：提供两个缓冲放大部分10A和10B，各个输入端子和输出端子共同连接。控制信号A被提供给MOSFET 13A和17A的栅极，并且控制信号A'分别被提供给MOSFET 16A和20A的栅极。控制信号B被提供给MOSFET 13B和17B的栅极，并且控制信号B'分别提供给MOSFET 16B和20B的栅极。在输出缓冲器5和CPU通过总线产生短路的情况下，由于由控制信号B和B'控制的缓冲放大部分10B是由传统的过量短路电流流过的时间非常短在更改地址信号后，只能运行一段规定的时间。

3. 发明专利

JPS59113590A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS59113590A
公开(公告)日：1984-06-30
申请号：JP22465482
申请日：1982-12-21
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： G11C11/417 , G11C11/34 , G11C11/409 , H01L27/10
CPC分类号： G11C11/34
摘要： PURPOSE:To reduce the short-circuit current in an output buffer without lowering the operation speed, by providing two buffer amplifying parts and controlling the operation of one buffer amplifying part in accordance with an output enable signal and grasping a detection data change in a sense amplifier to generate its delay signal. CONSTITUTION:One data D detected by a sense amplifier 4 is supplied to the gate of an MOSFET51, and an inverted signal DD' of a delayed signal DD is supplied to the gate of an MOSFET52 connected in series to the MOSFET51. The other data detected by the sense amplifier 4 is supplied to the gate of an MOSFET53. Even if an output buffer 5 and a CPU generate a short-circuit through a bus line similarly to a conventional circuit, the time when a conventional excessive short-circuit current is flowed is very short because a buffer amplifier 10B controlled by control signals B and B' is operated only for a prescribed time after the change of data.
摘要翻译：目的：为了降低输出缓冲器中的短路电流而不降低运行速度，通过提供两个缓冲放大部件，并根据输出使能信号控制一个缓冲放大部分的工作，并在某种意义上掌握检测数据变化放大器产生其延迟信号。构成：由读出放大器4检测到的一个数据D被提供给MOSFET51的栅极，延迟信号DD的反相信号DD'被提供给与MOSFET51串联连接的MOSFET52的栅极。由感测放大器4检测的其它数据被提供给MOSFET53的栅极。即使输出缓冲器5和CPU与常规电路类似地通过总线产生短路，由于由控制信号B和B控制的缓冲放大器10B，传统的过流短路电流流过的时间非常短 B'在数据更改之后只能运行一段规定的时间。

4. 发明专利

JPS59154692A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：JPS59154692A
公开(公告)日：1984-09-03
申请号：JP2877283
申请日：1983-02-23
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： G11C11/41 , G11C11/34 , G11C16/06 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To speed up data read speed by providing an MOS transister (TR) for discharging which discharges the charge on a data line coupled with plural memory cells so as to turn on an MOS TR7 when an address signal changes. CONSTITUTION:An MOS TR(Q)41 is connected between a circuit point S being an input terminal of a sense amplifier 36 and a reference potential point and an output signal from an NOR circuit 49 is inputted to its gate. Further, the output pulse from a pulse generating circuit 45 is inputted to the gate of a Q47 being a driving transistor to the NOR circuit 49 and the output signal from an inverter 44 is inputted to the gate of a Q48 being other driving TR respectively. Further, a signal at a connecting point between the Q46 and Q47, 48 in the NOR circuit 49 is inputted to the gate of the Q41 for discharge as an output signal in this circuit. A threshould voltage of said inverter 44 and a data sense level of the sense amplifier 36 are almost coincident with each other, then the discharge by the Q41 is attained in the vicinity of the sense level of the sense amplifier 36, thereby attaining the detection of data of the sense amplifier 36 in a short time.
摘要翻译：目的：通过提供放电的MOS转移器（TR）来加速数据读取速度，其中，在与多个存储单元耦合的数据线上放电，以便在地址信号改变时接通MOS TR7。构成：将MOS TR（Q）41连接在作为读出放大器36的输入端的电路点S与基准电位点之间，将来自NOR电路49的输出信号输入到其门。此外，来自脉冲发生电路45的输出脉冲被输入到NOR电路49的驱动晶体管的Q47的栅极，并且来自反相器44的输出信号分别输入到作为其他驱动TR的Q48的栅极。此外，在NOR电路49中的Q46与Q47,48之间的连接点处的信号作为该电路中的输出信号输入到用于放电的Q41的栅极。所述反相器44的检测电压和读出放大器36的数据感测电平几乎一致，则在读出放大器36的感测电平附近获得Q41的放电，从而实现检测在短时间内读出放大器36的数据。

5. 发明专利

JPS5966150A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS5966150A
公开(公告)日：1984-04-14
申请号：JP17718882
申请日：1982-10-08
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： SUZUKI KAZUTO , IWAHASHI HIROSHI , ASANO MASAMICHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/88
摘要： PURPOSE:To enable to prevent improper wirings due to stepwise disconnection of aluminum wirings by forming the upper or lower layer of the wirings in a 2- layer structure formed with wirings of polysilicon layer. CONSTITUTION:A contacting hole 14 opened at a diffused layer 12 is formed on an insulating film 13 formed of a silicon oxidized film of the upper surface of a wafer formed of the layer 12 in a substrate 11. An aluminum layer 20 is covered as the first conductive layer on the entire surface of the wafer, and a polysilicon layer 21 is further laminated as the second conductive layer on the layer 30, photoetched in the prescribed wiring pattern, and the wiring layer 22 of the 2- layer structure of the layers 20, 21 is formed. Thereafter, a PSG film 23 is covered as a protective film on the upper surface of the wafer, and a PSG film 23 and the layer 21 are photoetched to expose the layer 30 for bonding. In this manner, even if the layer 20 is stepwisely disconnected, the layer 21 of upper layer is formed uniformly along the surface of the contacting hole, and the whole wiring layer 22 is not entirely disconnected.
摘要翻译：目的：通过将布线的上层或下层形成为由多晶硅层的布线形成的2-层结构，能够防止由于铝布线的逐步断开引起的不正确布线。构成：在基板11的由层12形成的晶片的上表面的硅氧化膜形成的绝缘膜13上形成有在扩散层12开口的接触孔14，铝层20被覆盖在晶片的整个表面上的第一导电层和多晶硅层21作为第二导电层进一步层叠在层30上，在规定的布线图案中被蚀刻，并且层的2层结构的布线层22 20,21形成。此后，将PSG膜23作为保护膜覆盖在晶片的上表面，并且对PSG膜23和层21进行光刻，以露出用于接合的层30。以这种方式，即使层20逐步断开，上层的层21沿着接触孔的表面均匀地形成，并且整个布线层22没有完全断开。

6. 发明专利

JPS59113592A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：JPS59113592A
公开(公告)日：1984-06-30
申请号：JP22465682
申请日：1982-12-21
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： G11C11/417 , G11C11/34 , G11C11/409
CPC分类号： G11C11/34
摘要： PURPOSE:To attain a highly reliable semiconductor memory without malfunction shortening an access time in an output buffer part by providing two buffer amplifying parts and controlling the operation of one buffer amplifying part in accordance with an output enable signal and grasping the signal change of the output enable signal to generate its delay signal. CONSTITUTION:Two buffer amplifying parts which buffer-amplify detection data of a sense amplifier are provided, and one buffer amplifying part 10A is controlled in accordance with the output enable signal, and the other buffer amplifying part 10B is operated only for a prescribed time corresponding to the signal delay time of a delay circuit after the output enable signal is changed to an active state. A bus line is driven with the large driving force by the parts 10A and 10B, and one buffer amplifying part 10B is stopped in the stage where the logical level of the bus line is almost set, and the bus line is driven with the smaller driving force than before by the left buffer amplifying part 10A, thus shortening the access time practically.
摘要翻译：目的：为了获得高度可靠的半导体存储器，无需通过提供两个缓冲放大部件来缩短输出缓冲器部分的访问时间，并根据输出使能信号控制一个缓冲放大部分的操作，并且掌握输出信号的变化使能信号产生其延迟信号。构成：提供缓冲放大读出放大器的检测数据的两个缓冲放大部分，并根据输出使能信号控制一个缓冲放大部分10A，另一个缓冲放大部分10B只对规定时间进行操作与输出使能信号变为有效状态之后的延迟电路的信号延迟时间。总线通过部件10A和10B以较大的驱动力驱动，并且一个缓冲放大部分10B在总线线路的逻辑电平几乎被设置的阶段停止，并且总线线路用较小的驱动通过左缓冲放大部10A进行比较，从而实际上缩短了存取时间。

7. 发明专利

JP2010211922A Sense amplifier circuit 有权
标题翻译：感应放大器电路
公开(公告)号：JP2010211922A
公开(公告)日：2010-09-24
申请号：JP2010138331
申请日：2010-06-17
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , MATSUDA HIROYUKI , HONDA YASUHIKO , KATO HIDEO
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To enable high-speed reading by shortening an overcharge period. SOLUTION: The sense amplifier circuit includes: a current mirror circuit 1; a precharge circuit 2 and a load circuit 3 having output parts connected to the input part of the input circuit side of the current mirror circuit 1; and a precharge circuit 2R and a load circuit 3R having output parts connected to the input part of the comparison circuit side of the current mirror circuit 1. Counter capacitors 8 and 8R are disposed for canceling gate coupling of Pch transistors PTR2a and PRT2Ra constituting the precharge circuits 2 and 2R. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过缩短过充电期间来实现高速读取。解决方案：读出放大器电路包括：电流镜电路1; 预充电电路2和负载电路3，其输出部分连接到电流镜电路1的输入电路侧的输入部分; 以及预充电电路2R和负载电路3R，其输出部分连接到电流镜电路1的比较电路侧的输入部分。计数器电容器8和8R被设置用于抵消构成预充电的Pch晶体管PTR2a和PRT2Ra的栅极耦合电路2和2R。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2006101626A Four-phase clock driven charge pump circuit 有权
标题翻译：四相时钟驱动充电泵电路
公开(公告)号：JP2006101626A
公开(公告)日：2006-04-13
申请号：JP2004284119
申请日：2004-09-29
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , CHIN GIYOUSHIYOU , MATOBA SHINJI , KURIYAMA MASAO , KATO HIDEO
IPC分类号： H02M3/07 , H03K17/06 , H03K17/687
摘要： PROBLEM TO BE SOLVED: To provide a four-phase clock driven charge pump circuit that can operate at a high speed and enhance the pump capability. SOLUTION: A pump circuit is provided, and has n-channel transistors T12-T1(n+1), capacitors C1-Cn connected to drains of the n-channel transistors T12-T1(n+1) at one end, n-channel transistors T32-T3(n+1) having gates and drains mutually connected and also connected to one end of the capacitors C1-Cn, and having sources connected to gates of the n-channel transistors T12-T1(n+1), and capacitors Cm2-Cm(n+1) connected to the gates of the n-channel transistors T12-T1(n+1) at one end. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以高速运行并提高泵功能的四相时钟驱动电荷泵电路。解决方案：提供泵电路，并且具有n沟道晶体管T12-T1（n + 1），在一端连接到n沟道晶体管T12-T1（n + 1）的漏极的电容器C1-Cn 具有相互连接并且也连接到电容器C1-Cn的一端的栅极和漏极的n沟道晶体管T32-T3（n + 1），并且具有连接到n沟道晶体管T12-T1（n + 以及在一端连接到n沟道晶体管T12-T1（n + 1）的栅极的电容器Cm2-Cm（n + 1）。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2002150799A NON-VOLATILE MEMORY 审中-公开
公开(公告)号：JP2002150799A
公开(公告)日：2002-05-24
申请号：JP2001285039
申请日：2001-09-19
申请人： TOSHIBA CORP
发明人： NAKAI HIROTO , KATO HIDEO , ASANO MASAMICHI , TOKUSHIGE KAORU , YAMAMURA TOSHIO
IPC分类号： G11C16/02 , G11C29/00 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To specify a write-in defective bit line. SOLUTION: This memory has a non-volatile memory cell array, an address buffer storing an address externally inputted, a decoder selecting plural non- volatile memory cells from the memory cell array in accordance with an address stored in the address buffer, a data register to which data from the plural non-volatile memory cells selected by the decoder is inputted and outputting these inputted data, plural external control signal input terminals, and data input/output terminals connected to the data register and the address buffer, a command input mode decided in accordance with combination of plural external control signals is permitted, when a register read-command is inputted to the input/output terminal in this command input mode, contents of the address buffer are outputted to the input/output terminal.

10. 发明专利

JP2002133889A NON-VOLATILE SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：JP2002133889A
公开(公告)日：2002-05-10
申请号：JP2001284967
申请日：2001-09-19
申请人： TOSHIBA CORP
发明人： NAKAI HIROTO , KATO HIDEO , ASANO MASAMICHI , TOKUSHIGE KAORU , YAMAMURA TOSHIO
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To reduce circuit scale. SOLUTION: This memory has a decoding circuit selecting a memory cell from a non-volatile memory cell, a binary counter to which a flip-flop is connected in series, an address buffer generating an internal row address signal and an internal column address signal inputted to the decoding circuit, a first control terminal to which a first external control signal is inputted, plural input/output terminals, and an address input control means making a flip-flop store an external address inputted from the input/output terminal as an initial value responding to the first external control signal, the binary counter has a first flip-flop group supplying an internal row address signal to the row decoder, and a second flip-flop group supplying an internal column signal to a column decoder, the number of flip-flop of the second group is made the same as the number of input/output terminals.

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