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1. 发明专利

JP2014127641A Memory device 有权
标题翻译：内存设备
公开(公告)号：JP2014127641A
公开(公告)日：2014-07-07
申请号：JP2012284823
申请日：2012-12-27
申请人： Toshiba Corp , 株式会社東芝
发明人： FURUHASHI HIRONOBU , KUNISHIMA IWAO , SHUDO SUSUMU , ASAO YOSHIAKI , SUDO TAKESHI
IPC分类号： H01L27/105 , G11C13/00 , H01L45/00
CPC分类号： G11C13/0002 , G11C11/5678 , G11C13/0004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/065 , H01L45/1233 , H01L45/144
摘要： PROBLEM TO BE SOLVED: To provide a memory device that has high recording density.SOLUTION: A memory device according to the present invention comprises an n (n is an integer of 2 or greater) number of resistance variation films connected to each other in series. Each resistance variation film is a superlattice film in which a plurality of pairs of first crystalline layer composed of a first compound and second crystalline layer composed of a second compound are alternately arranged in layers. In the n number of resistance variation films, the average compositions of all the resistance variation films or the arrangement periods of the first and second crystalline layers are different from each other.
摘要翻译：要解决的问题：提供具有高记录密度的存储器件。解决方案：根据本发明的存储器件包括串联连接的电阻变化膜的n（n为2以上的整数）数量的电阻变化膜。每个电阻变化膜是超晶格膜，其中由第一化合物构成的多对第一结晶层和由第二化合物构成的第二晶体层交替排列。在n个电阻变化膜中，所有电阻变化膜的平均组成或第一和第二结晶层的排列周期彼此不同。

2. 发明专利

JP2013183085A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2013183085A
公开(公告)日：2013-09-12
申请号：JP2012046810
申请日：2012-03-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803 , H01L29/66818
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a highly-reliable semiconductor device.SOLUTION: A method for manufacturing a semiconductor device according to an embodiment comprises the steps of: manufacturing a structure in which a fin extending in a first direction is formed on an upper surface of a semiconductor substrate, a lower mask member and an upper mask member are provided on the fin, and the width of the upper mask member is wider than the widths of the fin and the lower mask member; implanting an impurity into the semiconductor substrate using the upper mask member and the lower mask member as a mask; removing the upper mask member; forming a gate insulating film on a side surface of the fin; forming a conductive film covering the fin and the lower mask member; forming a gate mask in which a pattern extending in a second direction is formed on the conductive film; and forming a gate electrode striding over the fin by etching the gate mask and the lower mask member as a mask.
摘要翻译：要解决的问题：提供一种用于制造高可靠性半导体器件的方法。解决方案：根据实施例的半导体器件的制造方法包括以下步骤：制造其中形成沿第一方向延伸的翅片的结构在半导体基板的上表面上，在翅片上设置下掩模构件和上掩模构件，上掩模构件的宽度比翅片和下掩模构件的宽度宽; 使用上掩模构件和下掩模构件作为掩模将杂质注入到半导体衬底中; 去除上面罩构件; 在所述翅片的侧面上形成栅极绝缘膜; 形成覆盖所述翅片和所述下掩模构件的导电膜; 形成栅极掩模，其中在所述导电膜上形成沿第二方向延伸的图案; 并且通过蚀刻栅极掩模和下掩模构件作为掩模来形成跨过鳍的栅电极。

3. 发明专利

JP2013055155A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2013055155A
公开(公告)日：2013-03-21
申请号：JP2011191048
申请日：2011-09-01
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8246 , H01L27/105 , H01L29/78 , H01L43/08
CPC分类号： H01L27/228 , H01L21/823431
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having uniform FinFET characteristics.SOLUTION: A manufacturing method of a semiconductor device according to an embodiment comprises the steps of: forming a recess in an upper layer part of a semiconductor substrate; disposing a sacrifice material in the recess; forming a plurality of fins which extend in one direction and are periodically arranged by selectively removing the semiconductor substrate and the sacrifice material; forming an element isolation insulating film below the space between the fins; removing the sacrifice material; forming a gate insulating film on an exposed surface of the fin; and forming a gate electrode which extends in a direction intersecting the one direction so as to stride over the fins on the element isolation insulating film.
摘要翻译：要解决的问题：提供具有均匀的FinFET特性的半导体器件的制造方法。解决方案：根据实施例的半导体器件的制造方法包括以下步骤：在半导体衬底的上层部分中形成凹部; 在牺牲品中放置牺牲物; 形成沿着一个方向延伸并且通过选择性地去除所述半导体衬底和所述牺牲材料而周期性布置的多个翅片; 在翅片之间的空间下方形成元件隔离绝缘膜; 去除牺牲物质; 在所述翅片的暴露表面上形成栅极绝缘膜; 以及形成在与所述一个方向相交的方向上延伸的栅电极，以跨越所述元件隔离绝缘膜上的所述鳍。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012169426A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2012169426A
公开(公告)日：2012-09-06
申请号：JP2011028660
申请日：2011-02-14
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L21/027 , G03F7/40 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/0338 , H01L21/0337 , H01L27/11526 , H01L27/11548 , H01L43/12 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To form patterns having different widths at the same time by a sidewall mask process.SOLUTION: A semiconductor device manufacturing method according to an embodiment comprises: a process of forming first and second core materials on a processed material 2; a process of forming a covering material having first and second layers 16a, 16b covering a top face and a lateral face of each of the first and the second core materials; a process of removing the second layer 16b covering the first core material; a process of forming a first sidewall mask having the first layer 16a on the lateral face of the first core material by etching the covering material and forming a second sidewall mask having the first and the second layers 16a, 16b on the lateral face of the second core material by etching the covering material; a process of removing the first and the second core materials; a process of simultaneously forming first and second patterns having different widths from each other by etching the processed material 12 using the first and the second sidewall masks as masks.
摘要翻译：要解决的问题：通过侧壁掩模工艺同时形成具有不同宽度的图案。解决方案：根据一个实施方案的半导体器件制造方法包括：在加工材料2上形成第一和第二芯材料的工艺; 形成覆盖材料的工艺，所述覆盖材料具有覆盖所述第一和第二芯材中的每一个的顶面和侧面的第一和第二层16a，16b; 去除覆盖第一芯材的第二层16b的工艺; 通过蚀刻覆盖材料形成具有第一层16a的第一层16a的第一侧壁掩模的工艺，并且形成具有第一和第二层16a，16b的第二侧壁掩模，第二侧壁掩模在第二通过蚀刻覆盖材料的芯材料; 去除第一和第二芯材料的过程; 通过使用第一和第二侧壁掩模作为掩模蚀刻处理材料12，同时形成彼此具有不同宽度的第一和第二图案的过程。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2010118599A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010118599A
公开(公告)日：2010-05-27
申请号：JP2008292206
申请日：2008-11-14
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L21/28 , H01L21/027 , H01L21/3213 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28123 , H01L21/0338 , H01L21/32139 , H01L29/4238
摘要： PROBLEM TO BE SOLVED: To suppress an increase of the number of steps or the like in a method for manufacturing a semiconductor device which performs gate processing by carrying out exposure processing for a plurality of times.
SOLUTION: A method of manufacturing a semiconductor device forms at least one pair of gate electrodes having end portions opposed to each other across a gap. The method includes forming a gate insulator (112) and a gate electrode layer (113x) on a substrate (111) in order, forming a first anti-reflection coating (201) and a first resist (202) on the gate electrode layer in order, exposing and developing the first resist, etching the gate electrode layer, using the first resist or the first anti-reflection coating as a mask, to remove the gate electrode layer from a region for forming the gap, thereby forming a hole (121) penetrating the gate electrode layer, forming a second anti-reflection coating (301) and a second resist (302) on the gate electrode layer where the hole has been formed, in order, exposing and developing the second resist, and etching the gate electrode layer, using the second resist (302) or the second anti-reflection coating (301) as a mask, to form, from the gate electrode layer, the at least one pair of gate electrodes (113) having the end portions opposed to each other across the gap.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过多次进行曝光处理来抑制进行门处理的半导体装置的制造方法中的台阶等的增加。解决方案：制造半导体器件的方法形成至少一对具有跨越间隙彼此相对的端部的栅电极。该方法包括在基板（111）上形成栅极绝缘体（112）和栅电极层（113x），以在栅电极层上形成第一抗反射涂层（201）和第一抗蚀剂（202）使用第一抗蚀剂或第一抗反射涂层作为掩模蚀刻栅极电极层，从形成间隙的区域去除栅极电极层，从而形成孔（121）），穿过所述栅极电极层，在形成有所述孔的所述栅极电极层上形成第二抗反射涂层（301）和第二抗蚀剂（302），以使所述第二抗蚀剂露出和显影，并蚀刻所述栅极电极层，使用第二抗蚀剂（302）或第二抗反射涂层（301）作为掩模，从栅极电极层形成至少一对栅电极（113），其具有与彼此跨越差距。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008124133A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008124133A
公开(公告)日：2008-05-29
申请号：JP2006304042
申请日：2006-11-09
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/336 , H01L21/768 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent excess etching in a shared contact region. SOLUTION: SiN liners used as DSLs are successively deposited in the shared contact region and are left as a laminate. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止共享接触区域中的过度蚀刻。解决方案：用作DSL的SiN衬垫依次沉积在共享接触区域中，并作为层压体留下。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007049166A Semiconductor device with close stress liner film, and method of manufacturing same 有权
标题翻译：具有闭合应力衬里膜的半导体器件及其制造方法
公开(公告)号：JP2007049166A
公开(公告)日：2007-02-22
申请号：JP2006218000
申请日：2006-08-10
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L29/786 , H01L21/336 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/6653 , H01L29/7843
摘要： PROBLEM TO BE SOLVED: To provide an FET having stress liners located closer to each other than a conventional FET with typical stress, and to provide its manufacturing method.
SOLUTION: A gate is formed on a silicon layer, and a pair of sidewall spacers are formed on both side surfaces that counter the gate. Using the sidewall spacers as a mask, ion implantation is performed for a pair of source/drain regions on the both sides of the opposite silicon layers. Furthermore, the wall side spacers are removed. After the removal of the wall side spacers, stress liners are formed so that the gate may be covered.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有比具有典型应力的常规FET更紧密的应力衬垫的FET，并提供其制造方法。解决方案：在硅层上形成栅极，并且在与栅极对置的两个侧表面上形成一对侧壁间隔物。使用侧壁间隔件作为掩模，对于相对硅层的两侧上的一对源极/漏极区域执行离子注入。此外，去除了壁侧间隔物。在去除壁侧间隔件之后，形成应力衬垫，使得可以覆盖浇口。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2014022688A Semiconductor device manufacturing method and semiconductor device 审中-公开
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：JP2014022688A
公开(公告)日：2014-02-03
申请号：JP2012162770
申请日：2012-07-23
申请人： Toshiba Corp , 株式会社東芝
发明人： ISHIBASHI SHOTA , ARAI SHINYA , SUDO TAKESHI
IPC分类号： H01L27/105 , H01L21/8246 , H01L45/00 , H01L49/00
CPC分类号： H01L21/823475 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has low contact resistance with a diffusion layer and less variation in contact resistance.SOLUTION: A manufacturing method according to the present embodiment comprises: forming an element isolation area and an active area on a surface of a semiconductor substrate; forming a plurality of gate electrodes above the active area; forming recesses sunken from the element isolation area in the active area by selectively etching the active area among the gate electrodes; depositing an interlayer insulation film on the active area, the element isolation area and the gate electrode; forming contact holes on the recesses by etching the interlayer insulation film by using anisotropic etching; enlarging a bottom face of each contact hole by further etching the interlayer insulation film on an inner wall of each contact hole by using isotropic etching; and forming contacts which contact recesses in the active area, respectively, by embedding conductive materials in the contact holes.
摘要翻译：要解决的问题：提供一种与扩散层具有低接触电阻和较小的接触电阻变化的半导体器件。解决方案：根据本实施例的制造方法包括：在表面上形成元件隔离区域和有源区域的半导体衬底; 在所述有源区上方形成多个栅电极; 通过选择性地蚀刻栅电极之间的有源区，形成从有源区域中的元件隔离区域凹陷的凹槽; 在有源区，元件隔离区和栅电极上沉积层间绝缘膜; 通过使用各向异性蚀刻蚀刻层间绝缘膜，在凹部上形成接触孔; 通过使用各向同性蚀刻进一步蚀刻每个接触孔的内壁上的层间绝缘膜来扩大每个接触孔的底面; 以及通过将导电材料嵌入到接触孔中来形成分别接触有源区域中的凹部的触点。

9. 发明专利

JP2013201277A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013201277A
公开(公告)日：2013-10-03
申请号：JP2012068473
申请日：2012-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/768 , H01L21/8246 , H01L23/522 , H01L27/105 , H01L29/78
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a fin-type semiconductor device that allows high integration and to provide a method of manufacturing the same.SOLUTION: A method of manufacturing a semiconductor device includes the steps of: forming a plurality of stripe-shaped gate electrodes that cover top surfaces and side surfaces of a stripe-shaped fin extending in a first direction and extend in a second direction crossing the first direction; ion-injecting an impurity into the side surfaces of the fin exposed between the plurality of gate electrodes; burying a first insulating layer between the plurality of gate electrodes to insulate the plurality of gate electrodes mutually; and forming a gate contact, via a second insulating layer, in the first insulating layer between the adjacent two gate electrodes of the plurality of gate electrodes to electrically connect the adjacent two gate electrodes.
摘要翻译：要解决的问题：提供一种允许高集成度并提供其制造方法的翅片型半导体器件。解决方案：制造半导体器件的方法包括以下步骤：形成多个条形栅电极其覆盖沿第一方向延伸并沿与第一方向交叉的第二方向延伸的条状翅片的顶表面和侧表面; 在所述多个栅电极之间暴露的所述鳍片的侧面离子注入杂质; 在所述多个栅电极之间埋设第一绝缘层，以使所述多个栅电极相互绝缘; 以及经由第二绝缘层在所述多个栅电极的相邻两个栅电极之间的所述第一绝缘层中形成栅极接触，以电连接所述相邻的两个栅电极。

10. 发明专利

JP2013183133A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2013183133A
公开(公告)日：2013-09-12
申请号：JP2012047956
申请日：2012-03-05
申请人： Toshiba Corp , 株式会社東芝
发明人： SUDO TAKESHI
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/112 , H01L29/78
CPC分类号： H01L21/0337 , H01L21/266 , H01L21/3086 , H01L21/76229 , H01L21/823431 , H01L21/823456 , H01L27/088 , H01L27/0886 , H01L29/6659
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of separately forming a fin-type transistor and a plane-type transistor.SOLUTION: A method for manufacturing a semiconductor device according to an embodiment comprises the steps of: forming a lower mask film on a semiconductor substrate; forming a barrier film in a first region; forming an upper mask film; removing the upper mask member from the first region and leaving the lower mask member, and removing the upper mask member and the lower mask member from the second region by performing etching under the condition that the etching speeds of the upper mask member and the lower mask member become faster than the etching speed of a barrier member; forming a conductive film; and selectively removing the conductive film by performing etching under the condition that the etching speed of the conductive film becomes faster than the etching speed of the lower mask member.
摘要翻译：要解决的问题：提供一种能够分别形成鳍型晶体管和平面型晶体管的半导体器件的制造方法。解决方案：根据实施例的半导体器件的制造方法包括以下步骤：半导体衬底上的下掩模膜; 在第一区域中形成阻挡膜; 形成上掩模膜; 从第一区域移除上掩模构件并离开下掩模构件，并且通过在上掩模构件和下掩模的蚀刻速度的条件下进行蚀刻从第二区域移除上掩模构件和下掩模构件构件变得比阻挡构件的蚀刻速度快; 形成导电膜; 并且在导电膜的蚀刻速度比下掩模构件的蚀刻速度快的条件下进行蚀刻来选择性地去除导电膜。

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