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1. 发明专利

JP2009201317A Method of controlling semiconductor device and electrostatic actuator 审中-公开
标题翻译：控制半导体器件和静电致动器的方法
公开(公告)号：JP2009201317A
公开(公告)日：2009-09-03
申请号：JP2008042908
申请日：2008-02-25
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYANO SHINJI
IPC分类号： H02N1/00 , B81B3/00 , H01H59/00
CPC分类号： H02N1/006
摘要： PROBLEM TO BE SOLVED: To simply and accurately determine an electrostatic actuator state and restore the state to a normal operating state promptly when the occurrence of charging and the like is determined.
SOLUTION: The hold voltage Vhold is applied to an upper electrode 14, while the grounding voltage Vss is applied to a lower electrode 15, and subsequently the voltage BE on the lower electrode 15 is used as the test voltage Vtest to separate the hold voltage Vhold on the upper electrode 14 so that the voltage TE on the upper electrode 14 may be placed in a high impedance state (hi-Z). A potential difference between the upper electrode 14 and the lower electrode 15 becomes Vhold-Vtest=Vmon. Thereafter, the voltage BE is restored to the grounding voltage Vss. The capacity between the electrodes 14 and 15 is measured on the basis of a drop range of the voltage TE due to a capacitive coupling at such a time to determine the open or closed state.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了简单而准确地确定静电致动器状态，并且当确定充电等的发生时，立即将状态恢复到正常操作状态。解决方案：将保持电压Vhold施加到上电极14，同时将接地电压Vss施加到下电极15，随后将下电极15上的电压BE用作测试电压V test，以将保持电压Vhold在上电极14上，使得上电极14上的电压TE可以被置于高阻抗状态（hi-Z）。上电极14和下电极15之间的电位差成为Vhold-Vtest = Vmon。此后，电压BE恢复到接地电压Vss。电极14和15之间的电容是在这样一个时间由于电容耦合的电压TE的下降范围而被测量的，以确定打开或关闭状态。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2007109366A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2007109366A
公开(公告)日：2007-04-26
申请号：JP2006226798
申请日：2006-08-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGAI TAKESHI , MIYANO SHINJI
IPC分类号： G11C11/406 , G11C11/401 , G11C29/42
CPC分类号： G06F11/106 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To simplify command input and control thereof and also to reduce a transition time from a normal operation mode to a data holding mode and a transition time from the data holding mode to the normal operation mode.
SOLUTION: When memory cells enter an operation mode which only holds data, a plurality of data are read out to generate and store a check bit for error detection and correction, and a refreshing is performed in a period within the error occurrence allowable range of an error correcting operation performed by the ECC circuits 16-1, 16-2 by using the check bit, and before the normal operation mode is restored from the operation mode which only holds data, a control circuit 17 performs control so that an error bit of the data is corrected by using the check bit. Then, in an entry/exit period, read/write and an ECC operation are sequentially performed for all the memory cells by a page mode operation, and also memory cells connected to a word line which is not accessed by the page mode operation, are sequentially activated and refreshed.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：简化其命令输入和控制，并且还减少从正常操作模式到数据保持模式的转换时间以及从数据保持模式到正常操作模式的转换时间。解决方案：当存储单元进入仅保存数据的操作模式时，读出多个数据以生成并存储用于错误检测和校正的校验位，并且在错误发生允许范围内的周期内进行刷新通过使用校验位由ECC电路16-1,16-2执行的纠错操作的范围，并且在从仅保存数据的操作模式恢复正常操作模式之前，控制电路17执行控制通过使用校验位来校正数据的错误位。然后，在入口/出口期间，通过页面模式操作对所有存储器单元顺序执行读/写和ECC操作，以及连接到未被页模式操作访问的字线的存储单元是顺序激活和刷新。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2003243528A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003243528A
公开(公告)日：2003-08-29
申请号：JP2002035681
申请日：2002-02-13
申请人： TOSHIBA CORP
发明人： YAMADA TAKASHI , SATO TSUTOMU , NITTA SHINICHI , NAGANO HAJIME , MIZUSHIMA ICHIRO , CHIKAMATSU NAOHITO , MINAMI YOSHIHIRO , MIYANO SHINJI , FUJII OSAMU
IPC分类号： H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device whose characteristic can be prevented from changing by stress. SOLUTION: The semiconductor device has a first semiconductor layer 13 provided on a semiconductor substrate 10 and connected electrically with the semiconductor substrate 10, a second semiconductor layer 12 provided near the semiconductor layer 13 and isolated electrically from the semiconductor substrate 10, and first and second transistors TR1, TR4 provided respectively on the first and second semiconductor layers 13, 12 and having gate electrodes 16a, 16d, respectively, provided in parallel with the boundary of the first and second semiconductor layers 13, 12. COPYRIGHT: (C)2003,JPO

4. 发明专利

JP2000133000A MEMORY HYBRID LOGIC LSI 失效
公开(公告)号：JP2000133000A
公开(公告)日：2000-05-12
申请号：JP30755898
申请日：1998-10-28
申请人： TOSHIBA CORP
发明人： FUKUDA MAKOTO , MIYANO SHINJI , BANBA HIRONORI , NAMEGAWA TOSHIMASA
IPC分类号： H01L21/822 , G01R31/28 , G01R31/3167 , G01R31/3185 , G11C29/02 , H01L21/82 , H01L27/04 , H01L27/10 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To shorten a test time and simplify a test by generating a plurality of memory macros and a macro ID for identifying the plurality of memory macros in one chip outside the plurality of memory macros, and electrically connecting one of the plurality of memory macros to an output pad. SOLUTION: At a selected memory macro, MEn=0 is input to a macro output control circuit 48 and an 8-bit output signal which is a direct selection of TDO(0-7) is output as an output signal DTDO(0-7) of the memory macro. At a non selected memory macro, MEn=1 is input to the macro output control circuit 48, and therefore the output signal DTDO(0-7) of the non selected memory macro is fixed to '1' irrespective of the 8-bit output signal TDO(0-7). The signal of '1' or '0' is fed to a logic part from the selected memory macro, and the output signal of '1' is fed from the non selected memory macro.

5. 发明专利

JPH10134022A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH10134022A
公开(公告)日：1998-05-22
申请号：JP29019296
申请日：1996-10-31
申请人： TOSHIBA CORP
发明人： SATO KATSUHIKO , MIYANO SHINJI
IPC分类号： G06F15/78 , G01R31/3185 , G11C5/02 , G11C11/401 , G11C29/12 , H01L21/822 , H01L27/04 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To reduce design burden in memory logic mixing LSI. SOLUTION: The main surface of an LSI chip 10 is occupied by a logic part 1, data input/output part 2 and memory macro part 3. The memory macro part 3 is arranged rectangular on the main surface of the LSI chip 10. A test control circuit 4 is arranged along one side of the memory macro part 3 inside the memory macro part 3. A data input/output circuit 5 is arranged along the other side of the memory macro part 3 inside the memory macro part 3. The test control circuit 4 can be arranged along one side of the LSI chip 10 as well. Test data are supplied from the test control circuit 4 through a data bus to the data input/output circuit 5.

6. 发明专利

JPH08139290A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08139290A
公开(公告)日：1996-05-31
申请号：JP27751194
申请日：1994-11-11
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , MIYANO SHINJI , NUMATA KENJI
IPC分类号： G11C11/401 , G11C7/06 , G11C7/10 , G11C8/12 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To provide a semiconductor memory in which the inversion of the data of a column not transferred can be prevented even when the number of the columns to be simultaneously transferred is large. CONSTITUTION: The semiconductor memory comprises a memory cell array 1, a sense amplifier group provided at each column, a driver precharger for activating the group, a data latch circuit group 3 provided at each column to temporarily store the data supplied from a DQ bus 20, and a transfer gate group 4 for simultaneously transferring the data stored in the group 3 to the amplifier group. The array 1 is divided into a plurality of blocks B1, B2 including desired number of columns, and the precharger is divided to a plurality of circuits 5-1 to 5-3 at the respective blocks B1, B2.

7. 发明专利

JPH07312084A CACHE MEMORY INCORPORATED MEMORY DEVICE 失效
公开(公告)号：JPH07312084A
公开(公告)日：1995-11-28
申请号：JP10388294
申请日：1994-05-18
申请人： TOSHIBA CORP
发明人： SATO KATSUHIKO , MIYANO SHINJI , YABE TOMOAKI , FURUYAMA TORU
IPC分类号： G11C11/409 , G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/407
摘要： PURPOSE:To realize high speed writing for a cache memory. CONSTITUTION:A initializing circuit 21 for a pair of data line is connected to a pair of data line DL, /DL. The initializing circuit 21 makes the pair of data line DL, /DL the same potential by short-circuiting or pre-charging. The initializing circuit 21 is controlled by an initialization control circuit 24. A first transfer gate 12 or a second transfer gate 13 is opened after short circuit or pre-charge of the pair of data line DL, /DL is finished, and data is written in a cache memory 11. The first transfer gate 12 is controlled by a control circuit 22, and the second transfer gate 13 is controlled by a column decoder (control circuit) 24.

8. 发明专利

JPH01132170A FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPH01132170A
公开(公告)日：1989-05-24
申请号：JP28947987
申请日：1987-11-18
申请人： TOSHIBA CORP
发明人： MIYANO SHINJI
IPC分类号： H01L21/338 , H01L29/10 , H01L29/778 , H01L29/812
摘要： PURPOSE:To obtain a new FET forming a channel in a homojunction interface and and the FET capable of being operated at high speed by a method wherein a first to a third individually specific semiconductor layers, a specific control gate, a specific source region, a specific drain region and the specific channel are provided. CONSTITUTION:The following are provided: a first semiconductor layer 11 of one conductivity type; a second semiconductor layer 12 which is formed on it and contains an impurity of the opposite conductivity type; a third semiconductor layer 13 which is formed on it, which is composed of a semiconductor material identical to that of the second semiconductor layer 12 and whose impurity concentration value is lower than that of the second semiconductor layer 12; a control gate 14 formed on it; a source region 15 and a drain region 16 which are formed by sandwiching the control gate 14; a channel 19 constituted by a potential well at an interface part between said second semiconductor layer 12 and said third semiconductor layer 13. For example, a P type GaAs layer 11, an n-type GaAs layer 12 and an undoped GaAs layer 13 are laminated; a Schottky gate electrode 14 is formed; after that, n type GaAs source and drain regions 15, 16 are formed.

9. 发明专利

JP2001004712A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH MIXED MEMORY AND METHOD FOR TESTING THE SAME 失效
公开(公告)号：JP2001004712A
公开(公告)日：2001-01-12
申请号：JP17578399
申请日：1999-06-22
申请人： TOSHIBA CORP
发明人： FUKUDA MAKOTO , WADA OSAMU , MIYANO SHINJI
IPC分类号： H01L21/822 , G01R31/28 , G11C29/02 , G11C29/14 , G11C29/48 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To make the testing time of a semiconductor integrated circuit device with mixed memory as short as possible. SOLUTION: A semiconductor integrated circuit device is provided with a logic section 3, a memory macro 5 mixedly mounted on the same semiconductor substrate together with the logic section 3, and a test input terminal 20 for inputting a test signal composed of a test command or test data. The circuit device is also provided with a test circuit 10 having a test signal generator 4 which generates an output switching signal 15, and a test signal 17a for operating the memory macro 5 for test based on a test command and a switch circuit 16 which selectively outputs either one of the output 17b of the memory macro 5 which is operated for test by the test signal and test data in accordance with the output switching signal 15 and a test output terminal 21 which outputs the output of the switch circuit 16 to the outside upon receiving the output.

10. 发明专利

JP2000156085A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2000156085A
公开(公告)日：2000-06-06
申请号：JP33080298
申请日：1998-11-20
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , MIYANO SHINJI
IPC分类号： G11C11/407 , G11C7/10 , G11C11/34 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/409 , G11C11/41 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which data reading and writing time is reduced while constituting a small capacity memory macro by setting an optimum delay time in accordance with the capacity of the memory macro. SOLUTION: A delay circuit 122 is constituted of inverter circuits 122a to 122f and capacitors 122g to 122l. The delay time of the circuit 122 is set by switching switches SW11 to SW13 in accordance with the memory capacity of the memory macro. Since an optimum delay time is set in accordance with the memory capacity of the memory macro, the reading and writing operations of data are speeded up.

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