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1. 发明专利

JPH0896578A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0896578A
公开(公告)日：1996-04-12
申请号：JP19345295
申请日：1995-07-28
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , HAGA AKIRA , MIYANO SHINJI , SATO KATSUHIKO , NUMATA KENJI , FURUYAMA TORU
IPC分类号： G11C11/409 , G11C11/401 , G11C11/407
摘要： PURPOSE: To obtain a semiconductor storage device capable of enlarging operating margin and capable of optimizing data transferring timing with the clock signals within a wide frequency range. CONSTITUTION: A transfer gate 36 for performing the transfer of data between a data latch 37 and a sense-amplifier 13, transfer gate control circuits 34, 35 for controlling the transfer gate and a sense-amplifier control circuit 23 for controlling the operation of the sense-amplifier are provided in the semiconductor storage device being a clock synchronous type and having the struture in which the data latch is provided. Then, at the time of writing data, after data are preliminarily latched in the data latch and data are supplied to bit line pair from the data latch by controlling the transfer gate with the transfer gate control circuit, the sense-amplifier is activated by the sense-amplifier control circuit. Thus, the matching between the timing of the activation of the sense-amplifier and the timing of the transfer of data can be obtained.

2. 发明专利

JPH04119652A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04119652A
公开(公告)日：1992-04-21
申请号：JP23890490
申请日：1990-09-11
申请人： TOSHIBA CORP
发明人： NUMATA KENJI
IPC分类号： H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enable a current level difference to be set large enough to serve as discriminating data by a method wherein a semiconductor device is provided with a discriminating circuit which contains a fuse element and a diode, and an impedance viewed from the standpoint of a connection node of a discriminating circuit toward an inner circuit is set larger than that toward the discriminating circuit. CONSTITUTION:A discriminating circuit 3 is composed of a fuse element 31 and a diode 32 connected in series between a connection node N and a power supply potential Vcc. On the other hand, a resistor R0 is an equivalent resistor of a wiring between an input pin 1 and the connection node N of the discriminating circuit, and a resistor Ra is an equivalent resistor of a wiring between the connection node N and the input circuit 2. An R1 is an equivalent resistor viewed from the connection node N toward the discriminating circuit 3 including the resistance of the fuse element 31. Apart from these resistors, an resistor Rb is a resistor which is inserted so as to enable a resistor, R2=Ra+Rb, viewed from the connection node N toward the input circuit 2 to be much larger than the equivalent resistor R1 toward a discriminating circuit 2 side. By this setup, discrimination data can be detected large enough in sensitivity, so that it can be discriminated that a redundant circuit system is utilized or not.

3. 发明专利

JPH03154287A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH03154287A
公开(公告)日：1991-07-02
申请号：JP29216289
申请日：1989-11-13
申请人： TOSHIBA CORP
发明人： NUMATA KENJI , FUJII HIDETAKE
IPC分类号： G11C11/401 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/12 , G11C11/409 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/41 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To increase the speed of operation and lower the consumption power ratio by providing a means which selects different potentials and drives a cell block selecting means, an I/O line, a low decoder, a column decoder, a data buffer, and a bit line I/O line. CONSTITUTION:A buffer 211 which possesses an I/O sense amplifier 111 are connected to I/O01, -I/O01 common to cell blocks CA0, CA1. A first pre-charger 131 which makes the I/O line pair to (1/2)Vcc as same as bit lines BL pair, and a second pre-charger 121 which make them Vcc are provided in a buffer 211. An I/O control circuit 141 selects and drives this I/O buffer 211 by a precharge control signal CEQ and a sense control signal. Selection signals -BSL1, -BSL0 are inputted to the control circuit 141, and when the CA0 or the CA1 are selected, precharger 131, 121 are turned on and off selectively and executes a (1/2)Vcc precharge, the standard potential of the sense amplifier 111 rises to Vcc, and the I/O line pair is also precharged to Vcc.

4. 发明专利

JPS6352444A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6352444A
公开(公告)日：1988-03-05
申请号：JP19522286
申请日：1986-08-22
申请人： TOSHIBA CORP
发明人： NUMATA KENJI
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To reduce the contacting resistance of a semiconductor integrated circuit device without increasing the area of the connecting parts of different wiring materials by providing a structure that the contacting surfaces of the connecting parts of the materials are bent. CONSTITUTION:A groove 10 of the size slightly larger than the twice of the thickness of a gate electrode material film deposited before depositing a gate electrode material 1 is formed in a field oxide film, and the material 1 is then deposited and worked. After an interlayer insulating film 11 is deposited and a connecting hole 4 is formed above the groove 10, an aluminum electrode material 2 is deposited. The thus formed structure contributes to increase in the contacting area S' of the wiring materials to reduce a contacting resistance. Similar effect can be obtained for the connection of other wirings, such as aluminum wirings.

5. 发明专利

JPS6341067A SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6341067A
公开(公告)日：1988-02-22
申请号：JP18458986
申请日：1986-08-06
申请人： TOSHIBA CORP
发明人： NUMATA KENJI , NAKAGAWA KAORU
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To inexpensively obtain a dynamic RAM having high reliability by overlapping a capacitor electrode and the gate electrode of an MOS transistor in a groove to be buried. CONSTITUTION:An Si3N4 film is deposited through a thermal oxide film on a p-type Si substrate 1 formed with a p-well by ion implantation, and patterned to form a field insulating film 2. Then, a first groove 3 is formed on a substrate 1. Then, a CVD oxide film is deposited, and etched back to bury an element separating insulating film 4 in the groove 2. A second groove 5 feeding in a direction Y is formed on the substrate 1 in the similar step. After a p type layer 6 is formed on the bottom of the second groove, it is thermally oxidized to form an oxide film, a CVD oxide film is deposited, and etched back to allow an element separating insulating film 7 to remain on the bottom of the groove 5. Thereafter, an n type layer 8 is formed on the sidewall of the groove 5, thermally oxidized to form a capacitor insulating film 9, while a capacitor electrode 10 is buried.

6. 发明专利

JPS62158359A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62158359A
公开(公告)日：1987-07-14
申请号：JP39686
申请日：1986-01-06
申请人： TOSHIBA CORP
发明人： NUMATA KENJI , YOKOYAMA SADAYUKI , OGURA ISAO
IPC分类号： H01L21/822 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To connect a drive circuit and a plurality of arrays, center lines thereof are displaced, without forming a wasteful region to the longer side length of a chip and using an oblique wiring by askew shaping one part of drive-circuit pattern block itself. CONSTITUTION:Decoders 121 and word-line drive circuits 122 for driving word lines in memory cells are shaped at the central section of a rectangular chip 11. Memory cell arrays 131 and 132 are each arranged at every two row along the shorter sides of the chip 11 in two regions divided by decoders 121, 122, and disposed under the state in which center lines along the longer sides of the chip 11 are displaced mutually. The displaced memory cell arrays 131, 132 are connected to the decoders 121 through the word-line drive circuits 122 by aslant forming the decoders 121. The central axes of the memory cell arrays 131, 132 and the central axes of patterns for the word-line drive circuits 122 are made parallel so that pattern sections being in contact with the memory cell arrays 131, 132 are not shaped askew positively at that time.

7. 发明专利

JPS6154714A Counter circuit 失效
标题翻译：计数器电路
公开(公告)号：JPS6154714A
公开(公告)日：1986-03-19
申请号：JP17626284
申请日：1984-08-24
申请人： Toshiba Corp
发明人： NUMATA KENJI
IPC分类号： H03K23/52 , H03K23/00
摘要： PURPOSE: To decrease deviation in the operation timing of a counter circuit composed of count-up circuits connected in plural series stages and to increase the operation margin, and reduce the power consumption by inserting a buffer circuit which charges and discharge a load capacitor into the output stage of each count-up circuit.
CONSTITUTION: Count-up data is set up with the 1st clock ϕ
2 and stored temporarily. Count-up data Va and Vb, and Qn and Qn are outputted with the 2nd clock ϕ
2 . Loads at points (a) and (b) are gate capacities of TRs 21,..., 26, and load capacities at the points (a) and (b) are much smaller than the load capacities of the Qn and Qn, so the loads are easily standardized. Therefore, the dimensions of a circuit 50 which counts up are easily reduced and standardized. Then, data at the points (a) and (b) are set up sufficiently while the clocks ϕ
1 and ϕ
2 are on with small current comsumption. Complementary data at the points (a) and (b) regard a ratioless type inveter, so there is no incontinent current and only the charging and discharging currents of the load capacitors are consumed.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：减少由多个串联级连接的反馈电路构成的计数器电路的运算时间偏差，增加运算余量，通过插入对负载电容进行充放电的缓冲电路来降低功耗每个递增电路的输出级。构成：使用第一个时钟phi2设置计数数据并暂时存储。计数数据Va和Vb以及Qn和Qn以第二时钟phi2输出。（a）和（b）点的载荷是TRs 21，...，26的栅极容量，而点（a）和（b）的负载能力远小于Qn和Qn的负载能力，所以负载容易标准化。因此，计数的电路50的尺寸容易降低和标准化。然后，在时钟phi1和phi2接通时，在点（a）和（b）处的数据被充分地建立，具有小的电流消耗。点（a）和（b）中的互补数据考虑到无性式的不动产，因此不存在失禁电流，仅消耗负载电容器的充电和放电电流。

8. 发明专利

JPH0358379A WORD LINE DRIVING CIRCUIT FOR DYNAMIC RAM 失效
公开(公告)号：JPH0358379A
公开(公告)日：1991-03-13
申请号：JP19284789
申请日：1989-07-26
申请人： TOSHIBA CORP
发明人： NUMATA KENJI , FUJII HIDETAKE
IPC分类号： G11C11/407
摘要： PURPOSE:To obtain a sufficient read/write margin and to secure reliability for a gate insulation film by dividing a capacitor for boost in a word line driving circuit into plural pieces, and limiting the potential of a word line at a prescribed value by driving them selectively. CONSTITUTION:When a row address strobe RAS goes to an L level and the word line driving circuit issues output, the capacitor 5 (51-53) for boost is charged while the output of a capacitor driving circuit 7 for boost is being set at the L level. When the output of the circuit 7 changes to an H level after the lapse of constant time, the capacitor 5 is driven sequentially, and an output node 10 is boosted. When a word line potential detection circuit 9 detects the fact that the potential of the node 10 arrives at a limitation potential set in advance, the output of the circuit 7 is stopped. Therefore, sufficient read/write can be performed in an area where source potential is low by obtaining a high boosting ratio, and the reliability for the gate insulation film can be secured in an area where the source potential is high.

9. 发明专利

JPS63224250A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63224250A
公开(公告)日：1988-09-19
申请号：JP5535687
申请日：1987-03-12
申请人： TOSHIBA CORP
发明人： NUMATA KENJI
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To provide a semiconductor storage device having high degree of integration and a decreased change-over region while employing folded arrangement for bit lines, by providing a word line on a gate electrode such that the word line jumps over a desired number of cell array block boundaries and is contacted with the gate electrodes at the block boundaries. CONSTITUTION:A pair of memory cells are provided in each semiconductor island region 1 and cell array blocks 2 are formed by partitioning in the 'low' direction. The cell array blocks 2 are arranged with deviation by one cell pitch and gate electrodes 6 of the memory cells are extended so as to be common to the blocks. A pair of bit lines BL of a sense amplifier S/A are arranged between the deviated cell array blocks 2. A word line 7 is provided on each gate electrode 6 by low-resistance wiring such that the word line 7 jumps over a desired number of block boundaries and is contacted with the gate electrodes 6 at the block boundaries. According to such constitution, there is no need of increasing the contact region and the cell array block 2 is allowed to have a relatively small width in the 'low' direction. Further, it is made possible to solve problems such as increase of a change-over region 3 and unbalanced capacitances of the bit lines BL.

10. 发明专利

JPS62159399A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62159399A
公开(公告)日：1987-07-15
申请号：JP39586
申请日：1986-01-06
申请人： TOSHIBA CORP
发明人： NUMATA KENJI
IPC分类号： G11C11/408 , G11C11/34
摘要： PURPOSE:To reduce diffusion layer resistance at a VSS side, and to improve an operating margin by preventing a decoder from being malfunctioned without sacrificing speed by putting the contact position of a VSS reference potential for a transistor between plural discharging control signal lines. CONSTITUTION:A reference potential line (VSS line) is arranged at the center part of a decoder pattern, not at the end part of it. In other words, the VSS line is arranged at the center part of the decoder pattern, and also between address lines An/2 and A'n/2. By adopting such a constitution, the increase in the number of wirings is prevented, and a distance between the VSS line and a discharging transistor located in the longest distance from the VSS line is reduced to L/2, and the sum R of the diffusion layer resistance at the VSS side can be reduced to a half.

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