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1. 发明专利

JPH118298A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH118298A
公开(公告)日：1999-01-12
申请号：JP17128397
申请日：1997-06-13
申请人： TOSHIBA CORP
发明人： OKAYAMA YASUNORI , MATSUOKA FUMITOMO , ISHIMARU KAZUNARI
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3205
摘要： PROBLEM TO BE SOLVED: To reduce scratches by providing a stopper film in a laminated structure that sandwiches, for example, an oxide film on an element formation region as a structure at planarizing. SOLUTION: A first deposited film 33, a second silicon oxide film 34, and a second deposited film 35 constitute a stopper film 3. Then, the second deposition film 35, the second silicon oxide film 34, and the first deposition film 33, the first silicon oxide film 2, and a semiconductor substrate 1 are successively etched, and a groove 5 where a bottom part reaches the inside of the semiconductor substrate 1 is formed. At that time, the depth of the groove 5 is set so that the breakdown voltage among wells becomes sufficiently large electrically, when an embedded element separation region is formed, and the stopper film 3 is a film for protecting the element formation region when flattening the irregularities of an embedded material, thus preventing damages due to scratches which are generated on the semiconductor substrate.

2. 发明专利

JPH04226054A SEMICONDUCTOR DEVICE HAVING MULTILAYERED INTERCONNECTION STRUCTURE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04226054A
公开(公告)日：1992-08-14
申请号：JP11265891
申请日：1991-02-20
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： MATSUOKA FUMITOMO , IKEDA NAOKI
IPC分类号： H01L21/768 , H01L23/29 , H01L23/522
摘要： PURPOSE:To provide a protection layer on the side wall of a first interconnection layer. CONSTITUTION:A first interconnection layer 13 is side-walled with an amorphous silicon layer 14 and spread with a silicon layer 15 so as to coat this first interconnection layer 13 and this amorphous silicon layer 14. This silicon oxide film 15 is pierced by a through hole 16 to expose a partial surface of the above- mentioned interconnection layer 13: this through hole 16 is filled with a tungsten layer 17, and the silicon oxide film 15 is overlaid with a second interconnection layer 18 partially connected to this tungsten layer 17.

3. 发明专利

JPS63248172A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63248172A
公开(公告)日：1988-10-14
申请号：JP8239587
申请日：1987-04-03
申请人： TOSHIBA CORP
发明人： MATSUOKA FUMITOMO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
摘要： PURPOSE:To attain the improvement of the insulating properties of a gate oxide film and the lowering of the resistance of an impurity diffusion layer without having an adverse effect on electrical characteristics by implanting ions, using a gate electrode consisting of a polycrystalline layer, etc., as a mask, forming the gate oxide film and substituting a metal for the gate electrode in an atmosphere containing the metal. CONSTITUTION:When ions are implanted to a semiconductor substrate 101, employing a gate electrode 108 composed of a polycrystalline layer, which is shaped onto an oxide film 104 on the substrate 101 and in which oxidation-resistant films are laminated, as a mask, impurity diffusion layers 107 are formed excellently because the mask is not shaped by a metallic layer. When the side face sections of the electrode 108 are oxidized and a polycrystalline section is oxidized, oxide films 110 as excellent insulating films, at edge sections of which film thickness is ensured sufficiently, are shaped. When the oxidation-resistant films are etched and a metallic gate electrode 112 is substituted for the gate electrode in an atmosphere including a metal, a sufficiently thick resistance metallic layer 113 is formed onto impurity diffusion layers 111 at the same time, thus preparing a semiconductor device in which the improvement of the insulating properties of a gate oxide film and the lowering of the resistance of the impurity diffusion layers are attained without having an effect on electrical characteristics.

4. 发明专利

JPH11340461A SEMICONDUCTOR DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH11340461A
公开(公告)日：1999-12-10
申请号：JP14773998
申请日：1998-05-28
申请人： TOSHIBA CORP
发明人： MATSUOKA FUMITOMO , KASAI KUNIHIRO
IPC分类号： H01L21/76 , H01L21/762 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To design a low capacity well in an element isolation using STI (shallow trench isolation) by preventing the occurrence of junction leakage between a heavily doped diffusion region and a well while suppressing punch through between elements. SOLUTION: A punch trough suppressing region 28 is formed only partially on the bottom 24a of a buried element isolation trench 24 while being self- aligned. More specifically, an STI trench is formed and a side wall is formed on the inner side face of the isolation trench 24 by leaving a silicon nitride film 26 selectively. Subsequently, ion implantation is performed and a punch through suppressing region 28 doped more heavily than the substrate in the vicinity thereof or a well with the same conductivity type is formed on the bottom region of the isolation trench 24.

5. 发明专利

JPH10178172A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH10178172A
公开(公告)日：1998-06-30
申请号：JP33693996
申请日：1996-12-17
申请人： TOSHIBA CORP
发明人： ISHIMARU KAZUNARI , MATSUOKA FUMITOMO , UMEZAWA KAORI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L21/28 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method by which the generation of ion implantation failures on the end of gate sidewall of an LDD(lightly doped drain) MOS transistor can be suppressed. SOLUTION: When implanting ions so as to form a source-drain region 8 of a MOS transistor, first and second sidewalls 6 are provided to a gate electrode 3. An impurity substance is implanted over the sidewalls, and after the second sidewall adjacent to the end of the source drain area to which impurities are implanted is removed, heat treatment is applied thereto for activating the impurities. Since a stress applied to the end of the high-concentration impurity implantation region which is changed to be amorphous is reduced by removing the second sidewall, the generation of failures on the end of the gate sidewall is suppressed, while the amorphous region is recrystallized through heat treatment. As a result, a semiconductor device having less gate leakage current, high performance and high reliability is obtained.

6. 发明专利

JPH06140501A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06140501A
公开(公告)日：1994-05-20
申请号：JP28869792
申请日：1992-10-27
申请人： TOSHIBA CORP
发明人： MORITA SHIGERU , MATSUOKA FUMITOMO , YOSHIMURA HISAO , MAEDA TAKEO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762
摘要： PURPOSE:To provide a semiconductor device having a buried region to separate an element, which has a shape sufficient to separate an element. CONSTITUTION:This semiconductor device has a silicon substrate 1 having a main surface, a groove 2 formed within the substrate 1, an extrusion 4 buried within the groove 2 and at the same time projecting from the main surface and a region to separate an element, which is composed of an insulating film formed in the shape of a slope 5a to 5c from the top of the extrusion 4 to the main surface of a base body. Since the region to separate an element makes a bulge with respect to the substrate 1, a depression formed along the side wall of the groove 2 is not present, and besides since it is formed in the shape of a slope from the top of the extrusion 4 to the main surface of the substrate 1, a part of difference in level is not present. Therefore, deposit is not left in the periphery of the region to separate an element, so that the risk of occurrence of defects, for instance, such as the short circuit of a gate can be relieved/.

7. 发明专利

JPH06112477A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06112477A
公开(公告)日：1994-04-22
申请号：JP25797592
申请日：1992-09-28
申请人： TOSHIBA CORP
发明人： MAEDA TAKEO , MATSUOKA FUMITOMO , ASANO YASUNORI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78 , H01L29/784 , H01L29/62
摘要： PURPOSE:To prevent not only a MOS transistor from deteriorating in characteristics but also a polycrystalline silicon layer and an impurity-doped region from increasing in contact resistance between them. CONSTITUTION:A first amorphous silicon layer is deposited on a gate oxide film 19, As ions are implanted into the first amorphous silicon layer located in an NMOS region 12, and B ions are implanted into the first amorphous silicon layer located in a PMOS region 11. Then, the first amorphous silicon layer is recrystallized through a thermal treatment into a first polycrystalline silicon layer 22 1mum to 3mum in grain diameter, a first WSi layer 23 is deposited on the polycrystalline silicon layer 22, and the first polycrystalline silicon layer 22 and the first WSi layer 23 are etched, whereby a first gate electrode 24 located in the NMOS region 12 and a second gate electrode 25 located in the PMOS region 11 are formed. Therefore, the polycrystalline silicon layer 22 can be prevented from deteriorating in impurity concentration.

8. 发明专利

JPH0277122A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0277122A
公开(公告)日：1990-03-16
申请号：JP7790589
申请日：1989-03-29
申请人： TOSHIBA CORP
发明人： MATSUOKA FUMITOMO
IPC分类号： H01L21/768 , H01L21/28 , H01L21/336 , H01L29/417 , H01L29/78
摘要： PURPOSE:To enable the connection of a diffusion layer region and a wiring part independent of conductivity types, and simplify a manufacturing process by a method wherein a connection hole to connect directly the wiring part and the diffusion layer region, and a connection hole with the wiring part are formed by selectively eliminating an interlayer insulating film. CONSTITUTION:A connection hole 9 to connect directly a wiring part 4b and a diffusion layer region 7b, a connection hole 10 with a diffusion layer region 7, and a connection hole 11 with a wiring part 4b are simultaneously formed through an interlayer insulating film 8. For each of the connection holes 9, 10 and 11, a tungusten film 12 and a metal wiring 13 are formed, thereby completing a semiconductor device. It is not necessary for a gate insulating film 3 to be eliminated in the region where the wiring part 4b and the diffusion layer region 7b are directly connected. There is the gate insulating film 3 between the wiring part 4b and the diffusion layer region 7b which are connected by a tungusten cover. Since this film 3 acts as a barrier for diffusion, it is not necessary to use the same conductivity type Si for the wiring part 4b and the diffusion layer region 7b, and the connection is enabled for either conductivity type.

9. 发明专利

JPS6384137A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6384137A
公开(公告)日：1988-04-14
申请号：JP23084786
申请日：1986-09-29
申请人： TOSHIBA CORP
发明人： MATSUOKA FUMITOMO , TOYOSHIMA YOSHIAKI
IPC分类号： H01L23/52 , H01L21/3205
摘要： PURPOSE:To prevent short circuits, by constituting Al wirings for transmitting one piece of information, which are provided between elements, with a plurality of split wirings, providing the width of each split wiring, which is located at the outermost part, as about 2 mum or less, and stopping hillocks at the outermost side even if the hillocks are yielded in the succeeding heat treatment. CONSTITUTION:A semiconductor element is formed on a semiconductor substrate. The entire surface including said element is covered with an insulating film composed of SiO2 and the like. A contact hole having a specified shape is provided by a photoetching method. Information transmitting wirings 1 and 2 composed of aluminum or aluminum alloy are embedded in the hole. The width of each of the wirings 1 and 2 is made to be about 10 mum so as to provide allowance for current capacity. An interval is made to be about 1 mum. In this constitution, the interconnections are divided in parallel. At the outsides of the divided interconnections 1a and 2a, which are located at the central parts and have the width of 10 mum, outer split wirings 1b and 2b having a width of 1mum are provided in parallel. In this constitution, even if hillocks 3 are yielded in the wirings 1b and 2b, they are stopped with the wirings 1b and 2b, and short circuits are not yielded in the wirings 1 and 2.

10. 发明专利

JPS62136857A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62136857A
公开(公告)日：1987-06-19
申请号：JP27814885
申请日：1985-12-11
申请人： TOSHIBA CORP
发明人： MATSUOKA FUMITOMO , TOYOSHIMA YOSHIAKI
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To realize a high integrity by a method wherein, after the 1st metal wiring is formed on a semiconductor substrate with the 1st insulating film between, the 2nd insulating film is formed over the whole surface and, after parts of the insulating film on the 1st metal wiring to form contact holes with diameters larger than the width of the wiring, the 2nd metal wiring is formed. CONSTITUTION:A heat oxide film 22 is formed on a silicon substrate 21 as a field insulating film to form an element region and an element isolation region. Then, after a semiconductor element is formed, a silicon oxide film 23 is formed on both of the regions and, after a W layer is formed, the W layer is etched with resist as a mask to form a metal wiring 24. Further, after a silicon nitride film 25 is formed over the whole surface, contact holes 26, which have diameters larger than the width of the metal wiring 24, are formed by etching. After that, an Al layer is deposited over the whole surface and etched to form a metal wiring 27 which are connected to the metal wiring 24 through the contact holes 26. With this constitution, restriction to the integrity around the contact holes can be avoided.

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