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1. 发明专利

JPH0714988A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0714988A
公开(公告)日：1995-01-17
申请号：JP14772093
申请日：1993-06-18
申请人： TOSHIBA CORP
发明人： MATSUOKA FUMITOMO , ASANO YASUNORI , KANEMURA TAKANAGA , MAEDA TAKEO
IPC分类号： H01L21/28 , H01L27/092
摘要： PURPOSE:To provide a fine and reliable CMOS device, by depositing a second conductive impurity containing a first conductive impurity all over, and removing the first and second silicon oxide films after the first and second conductive impurities are diffused in a polysilicon layer in a heat treatment step. CONSTITUTION:In a laminated structure, impurity doped polysilicon layers 10 and 11 and a tungsten silicide layer 12 are formed in a given shape to form a gate electrode, and source and drain regions for MOSFET are formed in an ion-implantation step. After a given layer insulating film is deposited, a given metalization step is carried out to complete a semiconductor device. Since a boundary part between the p-type polysilicon 10 and the n-type silicon layer 11 is fixed at a time in a self-alignment way in a photo engraving method, the distance (X or Y) to each channel region is hardly affected by an error in alignment as in a conventional way. Consequently, a reliable semiconductor device can be obtained.

2. 发明专利

JPH06112477A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06112477A
公开(公告)日：1994-04-22
申请号：JP25797592
申请日：1992-09-28
申请人： TOSHIBA CORP
发明人： MAEDA TAKEO , MATSUOKA FUMITOMO , ASANO YASUNORI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78 , H01L29/784 , H01L29/62
摘要： PURPOSE:To prevent not only a MOS transistor from deteriorating in characteristics but also a polycrystalline silicon layer and an impurity-doped region from increasing in contact resistance between them. CONSTITUTION:A first amorphous silicon layer is deposited on a gate oxide film 19, As ions are implanted into the first amorphous silicon layer located in an NMOS region 12, and B ions are implanted into the first amorphous silicon layer located in a PMOS region 11. Then, the first amorphous silicon layer is recrystallized through a thermal treatment into a first polycrystalline silicon layer 22 1mum to 3mum in grain diameter, a first WSi layer 23 is deposited on the polycrystalline silicon layer 22, and the first polycrystalline silicon layer 22 and the first WSi layer 23 are etched, whereby a first gate electrode 24 located in the NMOS region 12 and a second gate electrode 25 located in the PMOS region 11 are formed. Therefore, the polycrystalline silicon layer 22 can be prevented from deteriorating in impurity concentration.

3. 发明专利

JPH05326726A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05326726A
公开(公告)日：1993-12-10
申请号：JP12656292
申请日：1992-05-20
申请人： TOSHIBA CORP
发明人： ASANO YASUNORI
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/768 , H01L29/78 , H01L21/90 , H01L29/784
摘要： PURPOSE:To provide a self-aligned contact having no deterioration in reliability and destruction of a gate oxide film by plasma damage by a method wherein an insulating film is deposited on a member, a liquid-resisting layer deposited film is formed on a part of a member using a liquid-phase deposition method, and the liquid-resisting layer deposited film is removed. CONSTITUTION:A field oxide film 221 is formed on a silicon substrate 200, a gate oxide film 201 is formed on an element region, a polysilicon film 202 and an oxide film 203 are deposited thereon, and a resist 223 is patterned into a gate electrode. The resist is removed by conducting an anisotropic etching using the above-mentioned material as a mask, a gate electrode is formed, ions are implanted, and an oxide film is deposited thereon. A gate side-wall 204 is formed by conducting anisotropic etching on the whole surface, and a thin oxide film 207 is formed on the whole surface. Accordingly, the expected region for formation of a contact hole is patterned in such a manner that the resist is left, an oxide film 209 is deposited by a liquid-phase deposition method, and a self-aligned contact can be obtained without a contact RIF and a protective material forming process.

4. 发明专利

JP2004186475A Manufacture of semiconductor device 审中-公开
公开(公告)号：JP2004186475A
公开(公告)日：2004-07-02
申请号：JP2002352372
申请日：2002-12-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KUGIMIYA KENJI , MORITA SHIGERU , SONODA EIJI , ASANO YASUNORI , AMAI TAKASHI
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a method for reliably manufacturing a semiconductor device by controlling the resistance of a wiring layer.
SOLUTION: The method includes the steps of forming a first mask on a polycrystalline silicon layer and an Si substrate and then implanting an impurity of a first conduction type into an opening to form a first conduction type region; forming a second mask on the polycrystalline silicon layer and the Si substrate to overlap with the first mask, and then implanting an impurity of a second conduction type into the opening to form a second conduction type region separated from the first conduction type region; forming a metallic layer on the polycrystalline silicon layer and the Si substrate containing the first and second conduction type regions; and forming a silicide layer at an interface between the Si layer and the metallic layer.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2006019312A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2006019312A
公开(公告)日：2006-01-19
申请号：JP2004192394
申请日：2004-06-30
申请人： Toshiba Corp , 株式会社東芝
发明人： ASANO YASUNORI , MURAKAMI KATSUYA
IPC分类号： H01L23/52 , H01L21/3205
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05554 , H01L2924/01322 , H01L2924/14 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the separation of a film, such as an interlayer insulating film, and to improve bonding properties. SOLUTION: A semiconductor integrated circuit device comprises a plurality of wires formed in the interlayer insulating film laminated on a semiconductor substrate; a via for connecting the plurality of wires in the upper and lower directions; a bonding pad that is connected to at least one of the plurality of wires and has a bonding area for connecting a bonding wire for electrical connection to the outside; a plurality of reinforcing patterns that are formed in the interlayer insulating film at the lower section of the bonding pad and are not electrically connected to the bonding pad; and a via for reinforcement for connecting the reinforcement patterns arranged vertically in the plurality of reinforcement patterns. The reinforcement pattern is made of the same member as the plurality of wires, and at least one portion of the member directly below the bonding area has a part in which no member exist. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止诸如层间绝缘膜的膜的分离，并且改善粘合性能。解决方案：一种半导体集成电路器件，包括：层叠在半导体衬底上的层间绝缘膜中形成的多条导线; 通孔，用于在上下方向上连接多条电线; 接合焊盘，其连接到所述多个电线中的至少一个，并且具有用于将用于电连接的接合线连接到外部的接合区域; 多个加强图案，形成在所述接合焊盘的下部的所述层间绝缘膜中，并且不与所述接合焊盘电连接; 以及用于连接在多个加强图案中垂直设置的加强图案的加强用通孔。加强图案由与多个线材相同的构件制成，并且直接在接合区域下方的构件的至少一部分具有不存在构件的部分。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JPH04207054A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04207054A
公开(公告)日：1992-07-29
申请号：JP34030390
申请日：1990-11-30
申请人： TOSHIBA CORP
发明人： ASANO YASUNORI
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To prevent the release of gas from an interlayer insulation film into a connection hole in a thermal process by allowing a thin film to remain on a side wall of the interlayer insulation film and carrying out anisotropic etching so that the top of the interlaminar insulation film and the top of a first metal wiring on the bottom of the connection hole may be exposed. CONSTITUTION:A first metal wiring 3 is formed on a first interlayer insulation film 2. Then, a plasma SiO2 film is deposited as a second interlayer film 4. An SiO2 is further formed as a third interlaminar insulation film 5 in such a manner that moisture may be incorporated during the deposition. A plasma SiO2 film is deposited as a forth interlaminar film 6. Then, anisotropic etching is carried out so as to form a connection hole 8. When the connection hole is opened or after its opening work is ended, there is generated an insulation thin film 11 on the bottom of the connection hole (the surface of the first metal wiring 3). Then, a photoresist 7 is separated where there is deposited a thin film which contains no impurities, such as moisture on the whole surface of the fourth interlayer insulation film 6.

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