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1. 发明申请

WO2007117894A1 THERMAL PROCESSING FURNACE, GAS DELIVERY SYSTEM THEREFOR, AND METHODS FOR DELIVERING A PROCESS GAS THERETO 审中-公开
标题翻译：热处理炉，气体输送系统及其输送过程气体的方法
公开(公告)号：WO2007117894A1
公开(公告)日：2007-10-18
申请号：PCT/US2007/064461
申请日：2007-03-21
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , DIP, Anthony , MALSTROM, Eric, J.
发明人： DIP, Anthony , MALSTROM, Eric, J.
IPC分类号： C30B25/14 , C23C16/455
CPC分类号： H01L21/0214 , C30B25/14 , C30B31/16 , C30B35/00 , H01L21/02249 , H01L21/02255 , H01L21/28202 , H01L21/3145 , H01L21/324 , H01L21/67109 , Y10S438/935
摘要： A gas delivery system for supplying a process gas from a gas supply ( 14) to a thermal processing furnace (10), a thermal processing furnace (10) equipped with the gas delivery system, and methods for delivering process gas to a thermal processing furnace ( 10). The gas delivery system comprises a plurality of regulators (16, 18), such as mass flow controllers, in a process gas manifold (25) coupling a gas supply (14) with a thermal processing furnace (10). The regulators ( 16, 18) establish a corresponding plurality of flows of a process gas at a plurality of flow rates communicated by the process gas manifold (25) to the thermal processing furnace (10). The gas delivery system may be a component of the thermal processing furnace (10) that further includes a liner (38) that surrounds a processing space (26) inside the thermal processing furnace (10).
摘要翻译：一种用于从气体供应（14）向热处理炉（10）供应处理气体的气体输送系统，配备有气体输送系统的热处理炉（10）以及将工艺气体输送到热处理炉（10）。气体输送系统包括在将气体供应（14）与热处理炉（10）连接的工艺气体歧管（25）中的多个调节器（16,18），例如质量流量控制器。调节器（16,18）以由处理气体歧管（25）传递到热处理炉（10）的多个流速建立相应的多个处理气体流。气体输送系统可以是热处理炉（10）的组件，其还包括围绕热处理炉（10）内的处理空间（26）的衬套（38）。

2. 发明申请

WO2008100846A2 ATOMIC LAYER DEPOSITION SYSTEMS AND METHODS 审中-公开
标题翻译：原子层沉积系统和方法
公开(公告)号：WO2008100846A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/053561
申请日：2008-02-11
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , DIP, Anthony
发明人： DIP, Anthony
IPC分类号： C23C16/455
CPC分类号： C23C16/45551 , C23C16/45508 , C23C16/45519 , C23C16/45536 , C23C16/4584 , C23C16/54 , H01L21/68764 , H01L21/68771
摘要： Systems and methods for depositing thin films using Atomic Layer Deposition (ALD). The deposition system (10) includes a process chamber (16) with a peripheral sidewall (36), partitions (68, 70, 72, 74) that divide a processing space (38) inside the process chamber (16) into at least two compartments (76, 78), and a platter (50) that supports substrates (15) within the processing space (38). The platter (50) rotates the substrates (15) relative to the stationary peripheral sidewail (36) and compartments (76, 78). One compartment (76) receives a process material used to deposit a layer on each of the substrates (15) and the other compartment (78) contains an inert gas. A material injector (100, 100a, 100b), which injects the process materia!, communicates with the compartment (76) through the peripheral sidewall (36).
摘要翻译：使用原子层沉积（ALD）沉积薄膜的系统和方法
沉积系统（10）包括具有周边侧壁（36）的处理室（16），将处理室（16）内部的处理空间（38）分隔成至少两个隔室（76,78）以及支撑处理空间（38）内的基板（15）的浅盘（50）。盘片50使基板15相对于静止的周边侧壁36和隔室76,78旋转。一个隔室（76）接收用于在每个衬底（15）上沉积层的处理材料，而另一个隔室（78）包含惰性气体。注入处理材料的材料注射器（100,100a，100b）通过周边侧壁（36）与隔室（76）连通。

3. 发明申请

WO2007030194A1 BUILT-IN SELF TEST FOR A THERMAL PROCESSING SYSTEM 审中-公开
标题翻译：用于热处理系统的内置自检
公开(公告)号：WO2007030194A1
公开(公告)日：2007-03-15
申请号：PCT/US2006/026220
申请日：2006-07-06
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , KAUSHAL, Sanjeev , PANDEY, Pradeep , SUGISHIMA, Kenji , DIP, Anthony , SMITH, David , JOE, Raymond , GANDHI, Sundar
发明人： KAUSHAL, Sanjeev , PANDEY, Pradeep , SUGISHIMA, Kenji , DIP, Anthony , SMITH, David , JOE, Raymond , GANDHI, Sundar
CPC分类号： H01L22/10 , G05B23/0254 , H01L21/67248
摘要： A method of monitoring a thermal processing system (100, 200) in real-time using a built-in self test (BIST) table that includes positioning a plurality of wafers (W) in a processing chamber (202) in the thermal processing system (100, 200); executing a real-time dynamic model (330) to generate a predicted dynamic process response for the processing chamber (202) during the processing time; creating a first measured dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the measured dynamic process response; and comparing the dynamic estimation error to operational thresholds established by one or more rules in the BiST table.
摘要翻译：一种使用内置自检（BIST）表实时监测热处理系统（100,200）的方法，其包括将多个晶片（W）定位在热处理系统中的处理室（202）中（100,200）; 执行实时动态模型（330）以在处理时间期间生成用于处理室（202）的预测动态过程响应; 创建第一个测量动态过程响应; 使用预测的动态过程响应和测量的动态过程响应之间的差来确定动态估计误差; 并将动态估计误差与由BiST表中的一个或多个规则建立的操作阈值进行比较。

4. 发明申请

WO2007019449A1 IN-SITU ATOMIC LAYER DEPOSITION 审中-公开
标题翻译：现场原子层沉积
公开(公告)号：WO2007019449A1
公开(公告)日：2007-02-15
申请号：PCT/US2006/030735
申请日：2006-08-04
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , DIP, Anthony , SASAKI, Sadao , TOELLER, Michael , REID, Kimberly, G.
发明人： DIP, Anthony , SASAKI, Sadao , TOELLER, Michael , REID, Kimberly, G.
IPC分类号： C23C16/448 , C23C16/455 , C23C16/40 , H01L21/316
CPC分类号： H01L21/3141 , C23C16/0236 , C23C16/405 , C23C16/45546 , C23C16/45553 , C23C16/56 , H01L21/31645
摘要： An in situ method for forming a HfO2 high-k dielectric layer in a batch wafer processing system (1, 100). The method comprises first loading a plurality of wafers (40, 110) into a process chamber (10, 102), and then pre-treating the plurality of wafers (40, 110) in the process chamber (10, 102) with a first oxidizer. After pre-treating the wafers (40, 110), and without removing the wafers (40, 110) from the process chamber (10, 102), the method then comprises depositing HfO2 on the plurality of wafers (40, 110) by atomic layer deposition, which comprises a plurality of deposition cycles, each cycle comprising alternating exposure of the plurality of wafers (40, 110) in the process chamber (40, 110) to a second oxidizer and a hafnium precursor. The hafnium precursor is selected from hafnium tert-butoxide (HTB) or hafnium tetra-diethylamide (TDEAH).
摘要翻译：一种用于在间歇晶片处理系统（1,100）中形成HfO 2高k电介质层的原位方法。该方法包括首先将多个晶片（40,110）装载到处理室（10,102）中，然后用处理室（10,102）预处理处理室（10,102）中的多个晶片（40,110）氧化剂。在对晶片（40,110）进行预处理之后，并且不从处理室（10,102）移除晶片（40,110），然后该方法包括通过原子沉积多个晶片（40,110）上的HfO 2 层沉积，其包括多个沉积循环，每个循环包括将处理室（40,110）中的多个晶片（40,110）交替暴露于第二氧化剂和铪前体。铪前体选自叔丁醇铪（HTB）或四乙基铪铪（TDEAH）。

5. 发明申请

WO2008021598A1 THERMAL PROCESSING SYSTEM WITH IMPROVED PROCESS GAS FLOW AND METHOD FOR INJECTING A PROCESS GAS INTO A THERMAL PROCESSING SYSTEM 审中-公开
标题翻译：具有改进工艺流程的热处理系统和将工艺气体注入热处理系统的方法
公开(公告)号：WO2008021598A1
公开(公告)日：2008-02-21
申请号：PCT/US2007/068474
申请日：2007-05-08
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , DIP, Anthony , ASARI, Shinji , GANDHI, Meenakshisundaram
发明人： DIP, Anthony , ASARI, Shinji , GANDHI, Meenakshisundaram
IPC分类号： H01L21/00
CPC分类号： H01L21/67109 , C23C16/45578 , C23C16/45591 , H01L21/67098 , H01L21/67103 , H01L21/67115
摘要： A thermal processing system (10) with improved gas flow and method for injecting a process gas into a thermal processing system (10). The thermal processing system (10) has an injection section (50; 82) with injection outlets (52) that inject process gas into a processing space (14) and a delivery section (46; 81; 104) that delivers process gas to the injection section (50). The delivery section (46; 81; 104) may be coupled with the injection section (50; 82) at an inlet disposed between opposite ends (53, 53) of the injection section (50; 82). A fluid lumen (56) of the injection section (50; 82) may have a larger cross-sectional area than a fluid lumen (45) of the delivery section (46; 81; 104). The thermal processing system (10) may include an inner tube (12), which surrounds the processing space (14), having a slit (16) through which the processing space (14) communicates with an annular pumping space (72) defined between the inner tube (12) and an outer tube (12) of the thermal processing system (10).
摘要翻译：一种具有改善的气流的热处理系统（10）和将工艺气体注入热处理系统（10）的方法。热处理系统（10）具有注射部分（50; 82），其具有注入口（52），其将处理气体注入处理空间（14）和输送部分（46; 81; 104），其将处理气体输送到注射部分（50）。输送部分（46; 81; 104）可以在设置在喷射部分（50; 82）的相对端（53,53）之间的入口处与喷射部分（50; 82）联接。注射部分（50; 82）的流体腔（56）可以具有比输送部分（46; 81; 104）的流体腔（45）更大的横截面面积。热处理系统（10）可以包括围绕处理空间（14）的内管（12），其具有狭缝（16），处理空间（14）通过其与环形泵送空间（72）连通，内管（12）和热处理系统（10）的外管（12）。

6. 发明申请

WO2007117896A1 METHOD FOR REPLACING A NITROUS OXIDE BASED OXIDATION PROCESS WITH A NITRIC OXIDE BASED OXIDATION PROCESS FOR SUBSTRATE PROCESSING 审中-公开
标题翻译：基于氧化氮的氧化过程替代氧化镍基氧化工艺的方法，用于衬底加工
公开(公告)号：WO2007117896A1
公开(公告)日：2007-10-18
申请号：PCT/US2007/064464
申请日：2007-03-21
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , DIP, Anthony
发明人： DIP, Anthony
IPC分类号： H01L21/314 , H01L21/316
CPC分类号： H01L21/3143 , H01L21/0223 , H01L21/02233 , H01L21/02249 , H01L21/02255 , H01L21/28202 , H01L21/3144 , H01L21/31658 , H01L21/31662
摘要： A method for performing an oxidation process on a plurality of substrates in a batch processing system. According to one embodiment, the method includes selecting a N 2 O-based oxidation process for the substrates (16) including a first process gas containing N 2 O that thermally decomposes in a process chamber (12) of the batch processing system to N 2 , O 2 , and NO byproducts, and generating a replacement NO-based oxidation process for the substrates (16) including a second process gas containing N 2 , O 2 , and NO with molar concentrations that mimic that of the N 2 , O 2 , and NO byproducts in the N 2 O-based oxidation process. According to another embodiment of the invention, the NO-based oxidation process contains NO, O 2 , and an inert gas.
摘要翻译：一种在批处理系统中对多个基板进行氧化处理的方法。根据一个实施方案，该方法包括选择用于基材（16）的基于N 2 O O的氧化工艺，所述方法包括含有N 2 O 3的第一工艺气体，所述第一工艺气体在将分批处理系统的处理室（12）分配给N 2 O 2 O 2和NO副产物，并为基板（16）产生替代的基于NO的氧化工艺），其包括含有N 2 O 2 O 2的第二工艺气体和具有模拟N 2 O，O 2 <！ - SIPO - >和在N 2 O基氧化方法中的NO副产物。根据本发明的另一个实施方案，基于NO的氧化方法包含NO，O 2 H 2和惰性气体。

7. 发明申请

WO2005096358A1 A SILICON GERMANIUM SURFACE LAYER FOR HIGH-K DIELECTRIC INTEG RATION 审中-公开
标题翻译：用于高K介电整数的硅锗表面层
公开(公告)号：WO2005096358A1
公开(公告)日：2005-10-13
申请号：PCT/US2005/000661
申请日：2005-01-10
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , DIP, Anthony , ROY, Pradip, K. , KAUSHAL, Sanjeev , LEITH, Allen, J. , OH, Seungho , JOE, Raymond
发明人： DIP, Anthony , ROY, Pradip, K. , KAUSHAL, Sanjeev , LEITH, Allen, J. , OH, Seungho , JOE, Raymond
IPC分类号： H01L21/28
CPC分类号： H01L21/31604 , H01L21/02142 , H01L21/0217 , H01L21/02175 , H01L21/02318 , H01L21/02323 , H01L21/02337 , H01L21/02362 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/3185 , Y10T29/41
摘要： A method for using a silicon germanium (SiGe) surface layer (160) to integrate a high-k dielectric layer (180) into a semiconductor device. The method forms a SiGe surface layer (160) on a substrate (150) and deposits a high-k dielectric layer (180) on the SiGe surface layer (160). An oxide layer (170), located between the high-k dielectric layer (180) and an unreacted portion of the SiGe surface layer (160), is formed during one or both of deposition of the high-k dielectric layer (180) and an annealing process after deposition of the high-k dielectric layer (180). The method further includes forming an electrode layer (190) on the high-k dielectric layer (180).
摘要翻译：一种使用硅锗（SiGe）表面层（160）将高k电介质层（180）集成到半导体器件中的方法。该方法在衬底（150）上形成SiGe表面层（160），并在SiGe表面层（160）上沉积高k电介质层（180）。在高k电介质层（180）的沉积的一个或两个中，形成位于高k电介质层（180）和SiGe表面层（160）的未反应部分之间的氧化物层（170）沉积高k电介质层（180）后的退火工艺。该方法还包括在高k电介质层（180）上形成电极层（190）。

8. 发明申请

WO2005096352A2 SILICON-GERMANIUM THIN LAYER SEMICONDUCTOR STRUCTURE WITH VARIABLE SILICON-GERMANIUM COMPOSITION AND METHOD OF FABRICATION 审中-公开
标题翻译：具有可变硅 - 锗组合物的硅 - 锗薄层半导体结构及其制造方法
公开(公告)号：WO2005096352A2
公开(公告)日：2005-10-13
申请号：PCT/US2005/000916
申请日：2005-01-12
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , ROY, Pradip, K. , DIP, Anthony , LEITH, Allen, J. , OH, Seungho
发明人： ROY, Pradip, K. , DIP, Anthony , LEITH, Allen, J. , OH, Seungho
IPC分类号： H01L21/00
CPC分类号： H01L21/67109 , H01L21/0237 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/2807 , H01L29/161
摘要： A SiGe thin layer semiconductor structure containing a substrate (400, 500, 600) having a dielectric layer (410, 510, 610), a variable composition Si x Ge 1 - x layer (440, 520, 620) on dielectric layer (410, 510, 610), and a Si cap layer (450, 530, 630) on the variable composition Si x Ge 1x layer (440, 520, 620). The variable composition Si x Ge 1 - x layer (440, 520, 620) can contain a Si x Ge 1-x layer (520, 620) with a graded Ge content or a plurality of Si x Ge 1-x . sub-layers (420, 430) each with different Ge content (421, 431). In one embodiment of the invention, the SiGe thin layer semiconductor structure contains a semiconductor substrate (600) having a dielectric layer (610), a Si-containing seed layer (615) on the dielectric layer (610), a variable composition Si x Ge 1 - x layer (620) on the seed layer (615), and a Si cap layer (630) on the variable composition Si x Ge 1-x layer (620). A method and processing tool (1, 100) for fabricating the SiGe thin layer semiconductor structure are also provided.
摘要翻译：一种SiGe薄层半导体结构，其包含在电介质层（410,510,620）上具有介电层（410,510,610），可变组成物SixGe1-x层（440,520,620）的衬底（400,500,600） 610）和可变组成SixGe1x层（440,520,620）上的Si覆盖层（450,530,630）。可变成分SixGe1-x层（440,520,620）可以包含具有分级Ge含量或多个SixGe1-x的SixGe1-x层（520,620）。每个具有不同Ge含量的子层（420,430）（421,431）。在本发明的一个实施例中，SiGe薄层半导体结构包含在电介质层（610）上具有介电层（610），含Si种子层（615）的半导体衬底（600），可变组合物SixGe1- x2层（620）上，以及位于可变组成SixGe 1-x层（620）上的Si覆盖层（630）。还提供了一种用于制造SiGe薄层半导体结构的方法和处理工具（100）。

9. 发明申请

WO2007134035A2 IN-SITU FORMATION OF OXIDIZED ALUMINUM NITRIDE FILMS 审中-公开
标题翻译：氧化氮化铝膜的现场形成
公开(公告)号：WO2007134035A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/068447
申请日：2007-05-08
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , DIP, Anthony , REID, Kimberly, G.
发明人： DIP, Anthony , REID, Kimberly, G.
IPC分类号： C23C16/30 , C23C16/56
CPC分类号： C23C16/303 , C23C16/56
摘要： A method is provided for in-situ formation of a thin oxidized AlN film on a substrate. The method includes providing the substrate in a process chamber (10), depositing an AfN film on the substrate (40), and post-treating the AIN film with exposure to a nitrogen and oxygen-containing gas. The post-treating increases the dielectric constant of the AIN film with substantially no increase in the AIN film thickness. The method can also include pre-treating the substrate (40) prior to AIN deposition, post-anneaiing the AIN film before or after the post-treatment, or both.
摘要翻译：提供了一种在衬底上原位形成薄的氧化的AlN膜的方法。该方法包括在处理室（10）中提供衬底，在衬底（40）上沉积AfN膜，以及在暴露于含氮和含氧气体的情况下对AlN膜进行后处理。后处理增加了AIN膜的介电常数，而AlIN膜厚度基本上没有增加。该方法还可以包括在AIN沉积之前预处理衬底（40），在后处理之前或之后对AlN膜进行后处理或二者。

10. 发明申请

WO2005104207A1 METHOD FOR EXTENDING TIME BETWEEN CHAMBER CLEANING PROCESSES 审中-公开
标题翻译：用于在室间清洁过程之间延长时间的方法
公开(公告)号：WO2005104207A1
公开(公告)日：2005-11-03
申请号：PCT/US2005/002509
申请日：2005-01-26
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON AMERICA, INC. , JOE, Raymond , GUMPHER, John , DIP, Anthony
发明人： JOE, Raymond , GUMPHER, John , DIP, Anthony
IPC分类号： H01L21/318
CPC分类号： C23C16/4404 , H01L21/3185
摘要： A method for extending time between chamber cleaning processes in a process chamber (10, 102) of a processing system (1, 100). A particle-reducing film (502, 602, 608, 706) is formed on a chamber component (300, 500, 600, 700) in the process chamber (10, 102) to reduce particle formation in the process chamber (10, 102) during substrate processing, at least one substrate (40, 110) is introduced into the process chamber (10, 102) , a manufacturing process is performed in the process chamber (10, 102), and the at least one substrate (40, 110) is removed from the process chamber (10, 102). The particle-reducing film (502, 602, 608) may be deposited on a clean chamber component (300, 500, 600) or on a material deposit (302, 604) formed on a chamber component (300, 500, 600, 700). Alternatively, the particle-reducing film (706) may be formed by chemically modifying at least a portion of a material deposit (702) on a chamber component (700). The particle-reducing film (502, 602, 608, 706) may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.
摘要翻译：一种在处理系统（1,100）的处理室（10,102）中延长室清洁过程之间的时间的方法。在处理室（10,102）中的室部件（300,500,600,700）上形成颗粒减少膜（502,602,608,706），以减少处理室（10,102）中的颗粒形成），在处理室（10,102）中引入至少一个衬底（40,110），在所述处理室（10,102）中执行制造工艺，并且所述至少一个衬底（40,101） 110）从处理室（10,102）中取出。颗粒减少膜（502,602,608）可以沉积在清洁室部件（300,500,600）上或沉积在形成在腔室部件（300,500,600,700）上的材料沉积物（302,604）上）。或者，可以通过化学修饰室部件（700）上的材料沉积物（702）的至少一部分来形成颗粒还原膜（706）。颗粒减少膜（502,602,608,706）可以在每个制造过程之后形成，或者在多个制造过程之后以选定的间隔形成。

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