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1. 发明申请

WO2009027398A1 MASS STORAGE SYSTEM WITH IMPROVED USAGE OF BUFFER CAPACITY 审中-公开
标题翻译：改进了缓冲能力使用的大容量存储系统
公开(公告)号：WO2009027398A1
公开(公告)日：2009-03-05
申请号：PCT/EP2008/061148
申请日：2008-08-26
申请人： THOMSON LICENSING , ABELING, Stefan , MAAS, Johann , KLAUSBERGER, Wolfgang , BRUNE, Thomas
发明人： ABELING, Stefan , MAAS, Johann , KLAUSBERGER, Wolfgang , BRUNE, Thomas
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0658 , G06F3/0608 , G06F3/0656 , G06F3/0689
摘要： The present invention relates to a mass storage system (1) with improved usage of buffer capacity, and more specifically to a mass storage system (1) for real-time data storage with an embedded controller (2). According to the invention, the mass storage system (1) has a first data path between a real-time data interface (3) and a mass storage array (10), the first data path including a data buffer (7) without access latency, and a second data path between an embedded processor (2) and the mass storage array (10), wherein the data buffer (7) without access latency is also used as a data buffer for non real-time data transfers between the embedded processor (2) and the mass storage array (10).
摘要翻译：本发明涉及具有改进的缓冲容量使用量的海量存储系统（1），更具体地说，涉及一种用于利用嵌入式控制器（2）进行实时数据存储的海量存储系统（1）。根据本发明，大容量存储系统（1）具有在实时数据接口（3）和大容量存储阵列（10）之间的第一数据路径，第一数据路径包括没有访问延迟的数据缓冲器（7），以及嵌入式处理器（2）和大容量存储阵列（10）之间的第二数据路径，其中没有访问等待时间的数据缓冲器（7）也用作数据缓冲器，用于嵌入式处理器之间的非实时数据传输（2）和大容量存储阵列（10）。

2. 发明申请

WO2009024456A2 REDUNDANCY PROTECTED MASS STORAGE SYSTEM WITH INCREASED PERFORMANCE 审中-公开
标题翻译：具有提高性能的冗余保护大容量存储系统
公开(公告)号：WO2009024456A2
公开(公告)日：2009-02-26
申请号：PCT/EP2008/060257
申请日：2008-08-05
申请人： DEUTSCHE THOMSON OHG , ABELING, Stefan , KLAUSBERGER, Wolfgang , KOCHALE, Axel , BRUNE, Thomas
发明人： ABELING, Stefan , KLAUSBERGER, Wolfgang , KOCHALE, Axel , BRUNE, Thomas
IPC分类号： G06F11/10 , H04N5/00
CPC分类号： G06F11/1088 , G06F11/1076 , G06F2211/1016 , H04N21/2182 , H04N21/2318
摘要： The present invention relates to a redundancy protected mass storage system (1) with increased performance, and more specifically to a mass storage system (1) with multiple storage units (2). According to the invention, the resources that are essentially provided for compensating the damage of one or more storage units (2) are also used to enhance the system performance. For this purpose during reading or writing the storage system (1) just waits for the responses of a minimum number (n) of required storage units (2) to start reading or writing, respectively.
摘要翻译：本发明涉及一种性能提高的冗余保护海量存储系统（1），更具体地说涉及具有多个存储单元（2）的海量存储系统（1）。根据本发明，基本上提供用于补偿一个或多个存储单元（2）的损坏的资源也用于增强系统性能。为此，在读取或写入存储系统（1）期间，仅等待最小数量（n）所需存储单元（2）的响应开始读取或写入。

3. 发明申请

WO2012019997A1 STORING/READING SEVERAL DATA STREAMS INTO/FROM AN ARRAY OF MEMORIES 审中-公开
标题翻译：存储/读取存储/存储阵列中的几个数据流
公开(公告)号：WO2012019997A1
公开(公告)日：2012-02-16
申请号：PCT/EP2011/063619
申请日：2011-08-08
申请人： THOMSON LICENSING , KAMPHENKEL, Oliver , BRUNE, Thomas , DREXLER, Michael , ABELING, Stefan
发明人： KAMPHENKEL, Oliver , BRUNE, Thomas , DREXLER, Michael , ABELING, Stefan
IPC分类号： G06F12/02 , G06F13/16
CPC分类号： G06F12/0246 , G06F13/1684 , G06F2212/7202 , G06F2212/7203 , G06F2212/7208
摘要： High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO 1,..., FIFO Z) until the amount of collected data in a current buffer corresponds to a current one of the data blocks. Then, the data of the current data block from the current buffer are stored into memories connected to a current one of the memory buses, wherein the following buffered data block of the related data stream is later on stored into memories connected to a following one of the memory buses, the number of the following memory bus being increased with respect to the number of the current memory bus. These steps are repeated, also for the other ones of the data streams using other available ones of the buffers and other ones of the memory buses. In combination with a corresponding buffer control it is possible to allocate and use a minimum number of buffers in a flexible way.
摘要翻译：使用NAND闪速存储器（MDY.X）的高速大容量存储装置适用于在实时条件下记录和重放视频数据流，其中数据在闪速存储器中被逐页地处理并被并行写入多个内存总线（MBy）。然而，对于使用多个独立数据流进行操作，需要显着的缓冲区大小。根据本发明，来自不同数据流的数据被收集在相应的不同缓冲器（FIFO 1，...，FIFO Z）中，直到当前缓冲器中的收集数据量对应于当前的数据块。然后，将来自当前缓冲器的当前数据块的数据存储到连接到当前一个存储器总线的存储器中，其中相关数据流的后续缓冲数据块稍后被存储到连接到下一个存储器总线存储器总线，相对于当前存储器总线的数量增加了以下存储器总线的数量。重复这些步骤，对于使用缓冲器中的其他可用缓冲器和其它存储器总线的数据流中的其他步骤也是如此。结合相应的缓冲区控制，可以以灵活的方式分配和使用最少数量的缓冲区。

4. 发明申请

WO2010029079A1 METHOD FOR SYNCHRONIZING A RECEIVER AND A TRANSMITTER IN A COMMUNICATION SYSTEM, AND TRANSMITTING STATION AND RECEIVING STATION ADAPTED FOR USE IN THE METHOD ACCORDING TO THE INVENTION 审中-公开
标题翻译：用于在通信系统中同步接收机和发射机的方法，以及适用于根据本发明的方法的发射站和接收站
公开(公告)号：WO2010029079A1
公开(公告)日：2010-03-18
申请号：PCT/EP2009/061641
申请日：2009-09-08
申请人： THOMSON LICENSING , KROPP, Holger , SCHÜTZE, Herbert , BRUNE, Thomas
发明人： KROPP, Holger , SCHÜTZE, Herbert , BRUNE, Thomas
IPC分类号： H04J3/06 , H04H60/04
CPC分类号： H04J3/0664 , H04L7/0045 , H04L7/02
摘要： The method is used for synchronizing a transmitter (1) and a receiver (K0). The transmitter and the receiver operate at a first (f A ) or a third (f B ) clock frequency, respectively. The data generated by the transmitter (1) and the receiver (K 0 ) are transmitted in sections via a transmission link. The transmission link is operated in both directions at a second clock frequency (f prot ). The method comprises a step of clock synchronization between the transmitter and the receiver. To this end, an equalization method is used in which a transmission path (TXP) and a receiver path (RXP) respectively perform a clock cycle counting method, which comprises the following steps: the duration of a FRAME_VALID signal (DV), indicating a particular data transmission phase, in clock cycles of the first or the second clock frequency is ascertained in the transmission path; the duration of the FRAME_VALID signal (FV), indicating a particular data transmission phase, in clock cycles of the third or the second clock frequency is ascertained using a second counter (Z1', Z2') in the receiver path; the clock cycle numbers (ΔTX, ΔRX) respectively ascertained by the two counters are compared; the frequency difference between the operating clock (CLK_SRC) of the transmitter (1) and the operating clock (CLK_DEST) of the receiver (2) is equalized on the basis of the comparison result.
摘要翻译：该方法用于同步发射机（1）和接收机（K0）。发射机和接收机分别以第一（fA）或第三（fB）时钟频率工作。由发送器（1）和接收器（K0）生成的数据通过传输链路以部分的形式发送。传输链路以第二个时钟频率（fprot）在两个方向上工作。该方法包括发射机和接收机之间的时钟同步的步骤。为此，使用均衡方法，其中传输路径（TXP）和接收机路径（RXP）分别执行时钟周期计数方法，其包括以下步骤：FRAME_VALID信号（DV）的持续时间，指示在传输路径中确定在第一或第二时钟频率的时钟周期中的特定数据传输相位; 在第三或第二时钟频率的时钟周期中指示特定数据传输阶段的FRAME_VALID信号（FV）的持续时间使用接收机路径中的第二计数器（Z1'，Z2'）来确定; 分别由两个计数器确定的时钟周期数（？TX，？RX）进行比较; 基于比较结果，均衡发送器（1）的工作时钟（CLK_SRC）与接收器（2）的工作时钟（CLK_DEST）之间的频率差。

5. 发明申请

WO2003019361A3 METHODS AND DEVICE FOR INTERFACING COMMUNICATION BETWEEN DEVICES ON DIFFERENT NETWORKS 审中-公开
公开(公告)号：WO2003019361A3
公开(公告)日：2003-03-06
申请号：PCT/EP2002/009478
申请日：2002-08-22
申请人： THOMSON LICENSING SA , DEUTSCHE THOMSON-BRANDT GMBH , HENRY, Jean-Baptiste , BRUNE, Thomas
发明人： HENRY, Jean-Baptiste , BRUNE, Thomas
IPC分类号： G06F9/44
摘要： The invention concerns a 1. Method for interfacing communication between a first device (32) on a first network and a second device (35, 37) on a second network, the networks being connected by an interface device (31), the method being carried out by the interface device and being characterized by the steps of: detecting a first message on the first network, said first message being generated by the first device (32), said first message being relevant for the second device (35, 37); translating the first message into a format compatible with the second device (35, 37); sending a second message to the second device on the second network, the second message informing the second device that the first message has been detected; upon reception of a request from the second device, transmitting the translated first message. The invention also concerns a device for implementing the method.

6. 发明申请

WO2002035770A3 METHOD FOR THE DATA EXCHANGE BETWEEN NETWORK DEVICES 审中-公开
公开(公告)号：WO2002035770A3
公开(公告)日：2002-05-02
申请号：PCT/EP2001/011747
申请日：2001-10-11
申请人： THOMSON LICENSING S.A. , BRUNE, Thomas , HÜTTER, Ingo
发明人： BRUNE, Thomas , HÜTTER, Ingo
IPC分类号： H04L12/40
摘要： Two or more electronic devices are connected via a bus sys-tem (5) building a cluster or chain of devices (1, 3). A de-vice can be selected using a control device (1), wherein an user interface (6) for the selected device is generated based on description data which are stored in the selected device and are transferred to the control device. A single user interface is shown on a display of the control device which allows to operate at least two devices (1, 3) simulta-neously. The user interface of a first device is displayed as main user interface and the user interface of a second device is rendered within the main interface as reduced user interface (9) which includes only operation elements neces-sary for operation of the second device in combination with the first device.

7. 发明申请

WO2005059764A1 MEMORY CONTROLLER 审中-公开
标题翻译：内存控制器
公开(公告)号：WO2005059764A1
公开(公告)日：2005-06-30
申请号：PCT/EP2004/012940
申请日：2004-11-15
申请人： THOMSON LICENSING S.A. , NIGGEMEIER, Tim , BRUNE, Thomas , FREISSMANN, Lothar
发明人： NIGGEMEIER, Tim , BRUNE, Thomas , FREISSMANN, Lothar
IPC分类号： G06F13/16
CPC分类号： G06F13/18
摘要： The present invention relates to a memory controller (1) for an IC with an external DRAM (2), where the external DRAM (2) has at least one memory bank (21, 22, 23, 24) and communicates with the IC via at least one channel (6, 7, 8). In line with the invention, the memory controller (1) has a command scheduler (3) which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.
摘要翻译：本发明涉及一种用于具有外部DRAM（2）的IC的存储器控制器（1），其中外部DRAM（2）具有至少一个存储体（21,22,23,24），并且与IC经由至少一个通道（6,7,8）。根据本发明，存储器控制器（1）具有命令调度器（3），其基于用于命令的静态优先级分配和用于信道的动态优先级分配来对存储器组命令的传输进行优先级排序。

8. 发明申请

WO2008087082A1 METHOD AND APPARATUS FOR RECORDING DATA INTO A MATRIX OF MEMORY DEVICES 审中-公开
标题翻译：用于将数据记录到存储器件的矩阵中的方法和装置
公开(公告)号：WO2008087082A1
公开(公告)日：2008-07-24
申请号：PCT/EP2008/050213
申请日：2008-01-10
申请人： THOMSON LICENSING , DREXLER, Michael , BRUNE, Thomas
发明人： DREXLER, Michael , BRUNE, Thomas
IPC分类号： G11C29/00
CPC分类号： H04N5/907 , G06F11/073 , G06F11/0766 , G06F12/0246 , G11C29/76 , G11C29/82
摘要： For recording or replaying in real-time digital high band- width video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For the storage of streaming HD video data, NAND FLASH memory based systems can be used. Flash memory devices are physically accessed in a page oriented mode. Each flash device contains some static defect blocks which are already marked during production. Advantageously, by dealing with dynamic defect blocks during recording in a similar way, dynamic defects are handled like static defects. Thereby the file system remap tables can be searched to find spare blocks which are not marked as "bad blocks".
摘要翻译：用于实时数字高带宽视频信号的记录或重放。 HDTV，HD渐进式或高清胶片拍摄信号，需要非常快的记忆。对于流式传输高清视频数据的存储，可以使用基于NAND FLASH存储器的系统。闪存设备以页面定向模式进行物理访问。每个闪存设备都包含一些在生产过程中已经标记的静态缺陷块。有利地，通过以类似的方式处理记录期间的动态缺陷块，如静态缺陷那样处理动态缺陷。因此，可以搜索文件系统重映射表以找到未被标记为“坏块”的备用块。

9. 发明申请

WO2008028910A1 DEVICE FOR PROCESSING A STREAM OF DATA WORDS 审中-公开
标题翻译：用于处理数据字段的设备
公开(公告)号：WO2008028910A1
公开(公告)日：2008-03-13
申请号：PCT/EP2007/059245
申请日：2007-09-04
申请人： THOMSON LICENSING , BRUNE, Thomas , KAMPHENKEL, Oliver , SCHÜTZE, Herbert , WALDEN, Michael
发明人： BRUNE, Thomas , KAMPHENKEL, Oliver , SCHÜTZE, Herbert , WALDEN, Michael
IPC分类号： G06F13/40
CPC分类号： G06F13/4031
摘要： State of the art processor systems, esp. in embedded systems, are not able to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10G-Ethernet for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor. According to the invention it is proposed a kind of multiplexer architecture that is needed to split between control and data-path access for a PCI Express based architecture.
摘要翻译：最先进的处理器系统，尤其是在嵌入式系统中，无法在实时条件下处理数据，特别是吞吐率接近10 Gbps。因此，当使用PCI Express（PCIe）或Infiniband或10G以太网等接口进行10 Gbps数据吞吐量时，特殊数据路径必须处理高吞吐率数据。但是，诸如连接管理或时间不关键控制消息传递的任务更好地被处理器管理。根据本发明，提出了一种在基于PCI Express的架构的控制和数据路径访问之间分割所需的多路复用器架构。

10. 发明申请

WO2007080031A1 METHOD AND APPARATUS FOR RECORDING HIGH-SPEED INPUT DATA INTO A MATRIX OF MEMORY DEVICES 审中-公开
标题翻译：用于将高速输入数据记录到存储器件的矩阵中的方法和装置
公开(公告)号：WO2007080031A1
公开(公告)日：2007-07-19
申请号：PCT/EP2006/069265
申请日：2006-12-04
申请人： THOMSON LICENSING , BRUNE, Thomas , WITTENBURG, Jens, Peter
发明人： BRUNE, Thomas , WITTENBURG, Jens, Peter
IPC分类号： G11C16/10 , G11C29/00 , G06F12/12
CPC分类号： G11C16/10 , G11C29/76
摘要： For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data. In case an error occurred in the current page in one or more flash devices, the content of these current pages is kept in the additional memory buffer.
摘要翻译：用于在实时数字高带宽视频信号中进行记录或重放。 HDTV，HD渐进式或高清胶片拍摄信号，需要非常快的记忆。用于存储流式高清视频数据可以使用基于NAND FLASH存储器的系统。闪存设备以页面定向模式进行物理访问。根据本发明，将输入数据以多路复用方式写入多个闪存器件的矩阵中。执行尽可能简单和快速的列表处理，并且在矩阵架构内寻址单个闪存设备的闪存块的缺陷页面。当以顺序方式写入时，矩阵的所有闪存设备的当前闪存设备页面的数据内容被复制到附加存储器缓冲器中的相应存储区域。在当前系列页面已经无错误地写入闪存设备之后，附加存储器缓冲器中的相应存储区域被启用，以覆盖后续页面数据。如果一个或多个闪存设备中的当前页面发生错误，则这些当前页面的内容将保留在附加存储器缓冲区中。

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