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1. 发明申请

WO2008034027A3 PROCESSOR ARCHITECTURE FOR PROGRAMMABLE DIGITAL FILTERS IN A MULTI-STANDARD INTEGRATED CIRCUIT 审中-公开
标题翻译：多标准集成电路中可编程数字滤波器的处理器架构
公开(公告)号：WO2008034027A3
公开(公告)日：2008-09-12
申请号：PCT/US2007078439
申请日：2007-09-14
申请人： TEXAS INSTRUMENTS INC , SADAFALE MANGESH DEVIDAS , KRATOCHWIL KONRAD , KHASNIS HIMAMSHU GOPALAKRISHNA
发明人： SADAFALE MANGESH DEVIDAS , KRATOCHWIL KONRAD , KHASNIS HIMAMSHU GOPALAKRISHNA
IPC分类号： G06F17/17
CPC分类号： H03H17/0294 , H03H17/0223 , H03H17/0416 , H03H2218/10
摘要： An architecture for cascaded digital filters (104-1, 106-1 to 104-6, 106-6) comprises independently programmable controlling registers and independent interpolating factors (Il to 16); a digital to analog converter (108) for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter (106-1 to 106-6) property (filters order, coefficient symmetry, half- band, and poly-phase) can be programmed independently to support different system requirements and extract maximum throuput from a given hardware. The method of filtering digital signals comprises the steps of determining an interpolation factor of the cascaded digital filters with the lowest number of computations so as to match with the single sampling rate of the digital to analog converter, determining active filters and an interpolation factor of each digital filter in the cascaded digital filters, and determining a mode of operation of the cascaded digital filters.
摘要翻译：用于级联数字滤波器（104-1,106-1至104-6,106-6）的架构包括独立可编程控制寄存器和独立内插因子（Il至16）; 数模转换器（108），用于将数字信号转换成具有与级联数字滤波器的内插因子相匹配的恒定采样率的模拟信号。每个滤波器（106-1至106-6）的属性（滤波器顺序，系数对称，半频带和多相）可以独立编程，以支持不同的系统要求，并从给定的硬件中提取最大的输出。滤波数字信号的方法包括以下步骤：确定具有最低计算次数的级联数字滤波器的内插因子，以便与数模转换器的单采样率相匹配，确定有源滤波器和每个级联数字滤波器中的数字滤波器，以及确定级联数字滤波器的操作模式。

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