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1. 发明申请

WO2005109659A2 CONFIGURABLE DSL TRANSCEIVER 审中-公开
标题翻译：可配置DSL收发器
公开(公告)号：WO2005109659A2
公开(公告)日：2005-11-17
申请号：PCT/US2005015586
申请日：2005-05-04
申请人： TEXAS INSTRUMENTS INC , KRATOCHWIL KONRAD
发明人： KRATOCHWIL KONRAD
IPC分类号： H04B1/38 , H04B3/56
CPC分类号： H04L5/0064 , H04L1/0041 , H04L1/0065 , H04L5/0007 , H04L5/0042 , H04L5/0044 , H04L5/0082 , H04L27/3416
摘要： A DSL modem including a configurable digital transceiver (30) is disclosed. The digital transceiver (30) includes a configuration register (43), or other circuitry, that selects a number of analog transmission ports to be implemented in the modem. Instances of analog front-end circuitry for each of the configured ports are also provided. According to the disclosed embodiments, the number of ports supported is scaled with the data rate for each port, and with the signaling bandwidth for each port, to maximize the efficiency of the transmission.
摘要翻译：公开了一种包括可配置数字收发器（30）的DSL调制解调器。数字收发器（30）包括配置寄存器（43）或其他电路，其选择要在调制解调器中实现的多个模拟传输端口。还提供了每个配置端口的模拟前端电路的实例。根据所公开的实施例，所支持的端口的数量用每个端口的数据速率和每个端口的信令带宽进行缩放，以最大化传输的效率。

2. 发明申请

WO2005109659A3 CONFIGURABLE DSL TRANSCEIVER 审中-公开
公开(公告)号：WO2005109659A3
公开(公告)日：2005-11-17
申请号：PCT/US2005/015586
申请日：2005-05-04
申请人： TEXAS INSTRUMENTS INCORPORATED , KRATOCHWIL, Konrad
发明人： KRATOCHWIL, Konrad
IPC分类号： H04J3/16 , H04J3/22
摘要： A DSL modem including a configurable digital transceiver (30) is disclosed. The digital transceiver (30) includes a configuration register (43), or other circuitry, that selects a number of analog transmission ports to be implemented in the modem. Instances of analog front-end circuitry for each of the configured ports are also provided. According to the disclosed embodiments, the number of ports supported is scaled with the data rate for each port, and with the signaling bandwidth for each port, to maximize the efficiency of the transmission.

3. 发明申请

WO2008034027A2 PROCESSOR ARCHITECTURE FOR PROGRAMMABLE DIGITAL FILTERS IN A MULTI-STANDARD INTEGRATED CIRCUIT 审中-公开
标题翻译：用于多标准集成电路中可编程数字滤波器的处理器架构
公开(公告)号：WO2008034027A2
公开(公告)日：2008-03-20
申请号：PCT/US2007/078439
申请日：2007-09-14
申请人： TEXAS INSTRUMENTS INCORPORATED , SADAFALE, Mangesh, Devidas , KRATOCHWIL, Konrad , KHASNIS, Himamshu, Gopalakrishna
发明人： SADAFALE, Mangesh, Devidas , KRATOCHWIL, Konrad , KHASNIS, Himamshu, Gopalakrishna
IPC分类号： G06F17/17
CPC分类号： H03H17/0294 , H03H17/0223 , H03H17/0416 , H03H2218/10
摘要： An architecture for cascaded digital filters (104-1, 106-1 to 104-6, 106-6) comprises independently programmable controlling registers and independent interpolating factors (Il to 16); a digital to analog converter (108) for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter (106-1 to 106-6) property (filters order, coefficient symmetry, half- band, and poly-phase) can be programmed independently to support different system requirements and extract maximum throuput from a given hardware. The method of filtering digital signals comprises the steps of determining an interpolation factor of the cascaded digital filters with the lowest number of computations so as to match with the single sampling rate of the digital to analog converter, determining active filters and an interpolation factor of each digital filter in the cascaded digital filters, and determining a mode of operation of the cascaded digital filters.
摘要翻译：级联数字滤波器（104-1,106-1至104-6,106-6）的架构包括独立可编程控制寄存器和独立内插因子（II至16）; 数字到模拟转换器（108），用于以与级联数字滤波器的内插因子匹配的恒定采样速率将数字信号转换成模拟信号。每个滤波器（106-1至106-6）属性（滤波器阶数，系数对称，半带和多相）可以独立编程以支持不同的系统要求，并从给定硬件中提取最大的throuput。滤波数字信号的方法包括以下步骤：确定具有最少计算次数的级联数字滤波器的内插因子，以便与数模转换器的单个采样率相匹配，确定有源滤波器和每个滤波器的内插因子数字滤波器，以及确定级联数字滤波器的工作模式。

4. 发明申请

WO2008034027A3 PROCESSOR ARCHITECTURE FOR PROGRAMMABLE DIGITAL FILTERS IN A MULTI-STANDARD INTEGRATED CIRCUIT 审中-公开
标题翻译：多标准集成电路中可编程数字滤波器的处理器架构
公开(公告)号：WO2008034027A3
公开(公告)日：2008-09-12
申请号：PCT/US2007078439
申请日：2007-09-14
申请人： TEXAS INSTRUMENTS INC , SADAFALE MANGESH DEVIDAS , KRATOCHWIL KONRAD , KHASNIS HIMAMSHU GOPALAKRISHNA
发明人： SADAFALE MANGESH DEVIDAS , KRATOCHWIL KONRAD , KHASNIS HIMAMSHU GOPALAKRISHNA
IPC分类号： G06F17/17
CPC分类号： H03H17/0294 , H03H17/0223 , H03H17/0416 , H03H2218/10
摘要： An architecture for cascaded digital filters (104-1, 106-1 to 104-6, 106-6) comprises independently programmable controlling registers and independent interpolating factors (Il to 16); a digital to analog converter (108) for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter (106-1 to 106-6) property (filters order, coefficient symmetry, half- band, and poly-phase) can be programmed independently to support different system requirements and extract maximum throuput from a given hardware. The method of filtering digital signals comprises the steps of determining an interpolation factor of the cascaded digital filters with the lowest number of computations so as to match with the single sampling rate of the digital to analog converter, determining active filters and an interpolation factor of each digital filter in the cascaded digital filters, and determining a mode of operation of the cascaded digital filters.
摘要翻译：用于级联数字滤波器（104-1,106-1至104-6,106-6）的架构包括独立可编程控制寄存器和独立内插因子（Il至16）; 数模转换器（108），用于将数字信号转换成具有与级联数字滤波器的内插因子相匹配的恒定采样率的模拟信号。每个滤波器（106-1至106-6）的属性（滤波器顺序，系数对称，半频带和多相）可以独立编程，以支持不同的系统要求，并从给定的硬件中提取最大的输出。滤波数字信号的方法包括以下步骤：确定具有最低计算次数的级联数字滤波器的内插因子，以便与数模转换器的单采样率相匹配，确定有源滤波器和每个级联数字滤波器中的数字滤波器，以及确定级联数字滤波器的操作模式。

5. 发明专利

AT405470B Method and arrangement for the transmission of digital data 未知
公开(公告)号：AT405470B
公开(公告)日：1999-08-25
申请号：AT171997
申请日：1997-10-10
申请人： KRATOCHWIL KONRAD
IPC分类号： H04L1/00 , H03M7/00
摘要： The invention relates to a method and an arrangement for the transmission of digital data from a digital message source 1 via an encoder 4 and a data channel 3 to a digital message sink 2, connected upstream of which is a decoder 5 in which the data transmitted by the message source 1 are reconstructed, - where the states are determined in accordance with a trellis diagram in the decoder 5 according to a Viterbi algorithm, - where, for the state transitions originating from these states, the path metric γ is determined and the path with the smallest path metric γ is assumed to be correct, - where the minimum path metric γmin of the path metrics γ is determined, and - where, from each state reached, state transitions are pursued for the next time interval only when the path metric γ of this state does not exceed a predetermined limit value T relative to the minimum path metric γmin. The invention provides for a distance d between two trellis paths which is determined from the trellis diagram to be used for forming the limit value T.

6. 发明专利

ATA171997A 未知
公开(公告)号：ATA171997A
公开(公告)日：1998-12-15
申请号：AT171997
申请日：1997-10-10
申请人： KRATOCHWIL KONRAD
IPC分类号： H04L1/00 , H03M7/00
摘要： A Viterbi type decoder which discards paths with metrics more than a distance from the smallest metric with the distance determined by the smallest distance between paths in the trellis.

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