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1. 发明授权

US06566283B1 Silane treatment of low dielectric constant materials in semiconductor device manufacturing 有权
标题翻译：半导体器件制造中低介电常数材料的硅烷处理
公开(公告)号：US06566283B1
公开(公告)日：2003-05-20
申请号：US10073068
申请日：2002-02-12
申请人： Suzette K. Pangrle , Minh Van Ngo , Dawn Hopper , Lu You
发明人： Suzette K. Pangrle , Minh Van Ngo , Dawn Hopper , Lu You
IPC分类号： H01L2131
CPC分类号： H01L21/76831 , H01L21/31058 , H01L21/76802 , H01L21/76826
摘要： Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.
摘要翻译：通过在形成其之后的层之前用硅烷等离子体表面处理电介质层来形成改进的电介质层。实施例包括在低k电介质层中形成沟槽，并通过对电介质进行在PECVD室中产生的硅烷等离子体来修饰沟槽的侧表面。通过在包括电介质处理的侧表面的低k电介质上沉积共形阻挡层并在沟槽内沉积导电层来形成导电特征。

2. 发明授权

US06784095B1 Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing 有权
标题翻译：半导体器件制造中低介电常数材料的磷化处理
公开(公告)号：US06784095B1
公开(公告)日：2004-08-31
申请号：US10073066
申请日：2002-02-12
申请人： Suzette K. Pangrle , Minh Van Ngo , Dawn Hopper , Lu You
发明人： Suzette K. Pangrle , Minh Van Ngo , Dawn Hopper , Lu You
IPC分类号： H01L214767
CPC分类号： H01L21/76831 , H01L21/76826 , H01L21/76829
摘要： Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a phosphine plasma produced in PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a copper containing layer within the trench.
摘要翻译：通过在其上形成阻挡层之前用磷化氢等离子体表面处理电介质层来形成改进的电介质层。实施例包括在低k电介质层中形成沟槽，并通过对PECVD室中产生的磷化氢等离子体进行电介质修饰沟槽的侧表面。通过在包括电介质处理的侧表面的低k电介质上沉积共形阻挡层并在沟槽内沉积含铜层来形成导电特征。

3. 发明授权

US06836017B2 Protection of low-k ILD during damascene processing with thin liner 有权
标题翻译：在薄衬板加工过程中保护低k ILD
公开(公告)号：US06836017B2
公开(公告)日：2004-12-28
申请号：US10759170
申请日：2004-01-20
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/76807
摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
摘要翻译：通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用铜。

4. 发明授权

US06472336B1 Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material 有权
标题翻译：在沉积由腐蚀性材料构成的电介质之后形成封装层
公开(公告)号：US06472336B1
公开(公告)日：2002-10-29
申请号：US09511585
申请日：2000-02-23
申请人： Suzette K. Pangrle , Minh Van Ngo , Richard J. Huang
发明人： Suzette K. Pangrle , Minh Van Ngo , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/76801 , C23C16/401 , H01L21/31629 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer. An encapsulating layer is formed over the corrosive dielectric material on the first semiconductor wafer and on the reaction chamber to prevent contact of the corrosive dielectric material to any exposed structure of a second semiconductor wafer to be subsequently placed into the reaction chamber when such an exposed structure is reactive with the corrosive dielectric material.
摘要翻译：绝缘材料形成为围绕集成电路的互连结构。将第一半导体晶片放置在用于形成围绕第一半导体晶片上的集成电路的互连结构的绝缘材料的反应室中。沉积具有低介电常数的腐蚀介电材料以包围互连结构，并且腐蚀介电材料填充互连结构之间的任何间隙。在反应室内进行腐蚀性电介质材料的沉积，并且在第一半导体晶片上沉积腐蚀性电介质材料期间，腐蚀性电介质材料沉积在反应室上。在第一半导体晶片上和反应室上的腐蚀介质材料上形成封装层，以防止腐蚀性电介质材料与任何暴露的第二半导体晶片的结构接触，随后将其放置在反应室中，与腐蚀性介电材料反应。

5. 发明授权

US06291296B1 Method for removing anti-reflective coating layer using plasma etch process before contact CMP 有权
标题翻译：在接触CMP之前使用等离子体蚀刻工艺去除抗反射涂层的方法
公开(公告)号：US06291296B1
公开(公告)日：2001-09-18
申请号：US09416382
申请日：1999-10-12
申请人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
发明人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/951
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.
摘要翻译：本发明提供了一种从基板表面上的电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层，而不会在电介质层，形成在衬底上的源极/漏极区域的划伤和/或降解，以及形成在顶部的硅化物层堆叠门结构。 CH3F / O2蚀刻化学以比介电层，源/漏区和硅化物层的蚀刻速率明显更快的速率蚀刻ARC层。此外，通过在形成钨触点之前，通过用钨填充形成在电介质层中的接触开口来去除ARC层，消除了由于ARC层去除引起的钨触点的潜在划痕。

6. 发明授权

US06171947B2 Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines 失效
标题翻译：降低半导体互连线中应力诱发空隙的发生率的方法
公开(公告)号：US06171947B2
公开(公告)日：2001-01-09
申请号：US09209367
申请日：1998-12-08
申请人： Suzette K. Pangrle , Paul R. Besser , Minh Van Ngo , Stephan Keetai Park , Susan Tovar
发明人： Suzette K. Pangrle , Paul R. Besser , Minh Van Ngo , Stephan Keetai Park , Susan Tovar
IPC分类号： H01L2131
CPC分类号： H01L21/3145 , H01L21/76834
摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing. The pre-ILD annealing results in a substantially reduced incidence of stress-induced voiding in the underlying interconnect lines. Furthermore, the pre-ILD annealing can be combined with other advantageous process environments to more significantly reduce the incidence of stress-induced voiding in the underlying interconnect lines. Such combinations include process temperature reduction to below about 380 degrees Celsius and reduction of silane flow rate to less than about sixty standard cubic centimeters per minute.
摘要翻译：在用于在衬底的微电路互连线上形成层间电介质（ILD）涂层的方法中，衬底和互连线在沉积ILD之前被退火。通过使用等离子体增强化学气相沉积形成后退火SiON层。使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。等离子体反应形成沉积在半导体衬底上的SiON。此外，在沉积期间，对沉积温度和工艺压力进行微调，以控制SiON层的光学特性。测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。一旦形成了ILD，底物就可以进行进一步的处理。前ILD退火导致底层互连线中应力诱发的排泄的发生率显着降低。此外，前ILD退火可以与其他有利的工艺环境组合，以更显着地降低底层互连线中的应力诱发的排空的发生。这样的组合包括将工艺温度降低至低于约380摄氏度，并将硅烷流速降低至小于约60标准立方厘米每分钟。

7. 发明授权

US06746971B1 Method of forming copper sulfide for memory cell 有权
标题翻译：形成记忆电池用硫化铜的方法
公开(公告)号：US06746971B1
公开(公告)日：2004-06-08
申请号：US10314060
申请日：2002-12-05
申请人： Minh Van Ngo , Sergey D. Lopatin , Suzette K. Pangrle , Nicholas H. Tripsas , Hieu T. Pham
发明人： Minh Van Ngo , Sergey D. Lopatin , Suzette K. Pangrle , Nicholas H. Tripsas , Hieu T. Pham
IPC分类号： H01L2131
CPC分类号： H01L51/0036 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/28 , H01L51/0034 , H01L51/0035 , H01L51/0037 , H01L51/0038 , H01L51/0041 , H01L51/005 , H01L51/0053 , H01L51/0059 , H01L51/0077 , H01L51/0081 , H01L51/0084 , H01L51/0085
摘要： An organic memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元。可控导电介质包含有机半导体层和无源层。当施加外部刺激（例如施加的电场）时，可控导电介质改变其阻抗。还公开了制造有机存储器件/单元的方法，使用有机存储器件/单元的方法，以及诸如包含有机存储器件/单元的计算机的器件。

8. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

9. 发明授权

US06462417B1 Coherent alloy diffusion barrier for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干合金扩散屏障
公开(公告)号：US06462417B1
公开(公告)日：2002-10-08
申请号：US09772750
申请日：2001-01-29
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Pangrle
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76844 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76873 , H01L21/76886 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an alloy-barrier layer lining the channel opening, and a conductor core filling the channel opening. An alloy layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form an alloy-barrier to diffusion of the material of the conductor core to the channel dielectric layer. The alloy-barrier layer is reacted with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口，衬在沟道开口的合金阻挡层和填充沟道开口的导体芯。沉积合金层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成对导体芯的材料扩散到沟道介电层的合金阻挡层。合金阻挡层与导体芯和沟道电介质层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯在双重嵌入式集成电路中的芯体扩散。

10. 发明授权

US06723635B1 Protection low-k ILD during damascene processing with thin liner 有权
标题翻译：保护低k ILD在镶嵌加工与薄衬里
公开(公告)号：US06723635B1
公开(公告)日：2004-04-20
申请号：US10115245
申请日：2002-04-04
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
摘要翻译：通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用铜。

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