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1. 发明授权

US07981791B2 Thin films 有权
标题翻译：薄膜
公开(公告)号：US07981791B2
公开(公告)日：2011-07-19
申请号：US12202132
申请日：2008-08-29
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
IPC分类号： H01L21/4763
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了梯度栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

2. 发明申请

US20110256718A1 THIN FILMS 审中-公开
标题翻译：薄膜
公开(公告)号：US20110256718A1
公开(公告)日：2011-10-20
申请号：US13079562
申请日：2011-04-04
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
IPC分类号： H01L21/285
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了梯度栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

3. 发明授权

US07419903B2 Thin films 有权
标题翻译：薄膜
公开(公告)号：US07419903B2
公开(公告)日：2008-09-02
申请号：US11106220
申请日：2005-04-13
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey
IPC分类号： H01L21/4763
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了渐变栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝到氧化铝和较高介电材料（例如ZrO 2）的混合物变化为纯高k材料并返回到氧化铝。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

4. 发明申请

US20090068832A1 THIN FILMS 有权
标题翻译：薄膜
公开(公告)号：US20090068832A1
公开(公告)日：2009-03-12
申请号：US12202132
申请日：2008-08-29
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christrian J. Werkhoven
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christrian J. Werkhoven
IPC分类号： H01L21/4763
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了梯度栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

5. 发明申请

US20050181555A1 Thin films 有权
标题翻译：薄膜
公开(公告)号：US20050181555A1
公开(公告)日：2005-08-18
申请号：US11106220
申请日：2005-04-13
申请人： Suvi Haukka , Ivo Raaijmakers , Wei Li , Juhana Kostamo , Hessel Sprey , Christiaan Werkhoven
发明人： Suvi Haukka , Ivo Raaijmakers , Wei Li , Juhana Kostamo , Hessel Sprey , Christiaan Werkhoven
IPC分类号： C23C16/02 , C23C16/34 , C23C16/40 , C23C16/44 , C23C16/455 , C23C16/48 , C30B25/14 , H01L21/28 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L29/51 , H01L21/8238
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了梯度栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝到氧化铝和较高介电材料（例如ZrO 2）的混合物变化为纯高k材料并返回到氧化铝。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

6. 发明授权

US06759325B2 Sealing porous structures 有权
标题翻译：密封多孔结构
公开(公告)号：US06759325B2
公开(公告)日：2004-07-06
申请号：US10303293
申请日：2002-11-22
申请人： Ivo Raaijmakers , Pekka T. Soininen , Ernst Granneman , Suvi Haukka , Kai-Erik Elers , Marko Tuominen , Hessel Sprey , Herbert Terhorst , Menso Hendriks
发明人： Ivo Raaijmakers , Pekka T. Soininen , Ernst Granneman , Suvi Haukka , Kai-Erik Elers , Marko Tuominen , Hessel Sprey , Herbert Terhorst , Menso Hendriks
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/28562 , H01L21/7681 , H01L21/76814 , H01L21/7682 , H01L21/76825 , H01L21/76828 , H01L21/76831 , H01L21/76844 , H01L21/76864 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality. An alternating process can also be arranged by selection of pulse separation and/or pulse duration to achieve reduced conformality relative to a self-saturating, self-limiting atomic layer deposition (ALD) process. In still another arrangement, layers with anisotropic pore structures can be sealed by selectively melting upper surfaces. Blocking is followed by a self-limiting, self-saturating atomic layer deposition (ALD) reactions without significantly filling the pores.
摘要翻译：提供了用于集成电路中的双镶嵌结构的保形衬里的方法和结构，特别是在多孔材料中形成的开口。沟槽和接触通孔形成在绝缘层中。沟槽和通孔的侧壁上的孔堵塞，然后将结构暴露于交替的化学物质以形成所需衬里材料的单层。在示例性工艺流程中，密封层的化学或物理气相沉积（CVD或PVD）由于不完美的共形性而堵塞孔。也可以通过选择脉冲分离和/或脉冲持续时间来布置交替过程，以相对于自饱和的自限制性原子层沉积（ALD）工艺实现降低的共形。在另一种布置中，可以通过选择性地熔化上表面来密封具有各向异性孔结构的层。之后是自限制的，自饱和的原子层沉积（ALD）反应而没有显着填充孔隙。

7. 发明申请

US20120015105A1 METHOD OF CVD-DEPOSITING A FILM HAVING A SUBSTANTIALLY UNIFORM FILM THICKNESS 有权
标题翻译： CVD沉积具有大量均匀薄膜厚度的薄膜的方法
公开(公告)号：US20120015105A1
公开(公告)日：2012-01-19
申请号：US13183016
申请日：2011-07-14
申请人： Maarten Stokhof , Hessel Sprey , Yoshimi Tatsuya , Bert Jongbloed , Noureddine Adjeroud
发明人： Maarten Stokhof , Hessel Sprey , Yoshimi Tatsuya , Bert Jongbloed , Noureddine Adjeroud
IPC分类号： C23C16/52 , C23C16/455
CPC分类号： C23C16/34 , C23C16/45523
摘要： Method of depositing a film having a substantially uniform thickness by means of chemical vapor deposition, comprising: providing a reaction chamber; providing a substrate in said reaction chamber; subjecting the substrate to a series of deposition cycles, wherein each deposition cycle includes the steps of: (a) during a first time interval, supplying a first reactant to the reaction chamber; (b) during a second time interval, supplying a second reactant to the reaction chamber; and (c) during a third time interval, supplying neither the first nor the second reactant to the reaction chamber; wherein a start of the second time interval lies within the first time interval, such that a pre-exposure interval exists between a start of the first time interval and the start of the second time interval, during which pre-exposure interval the first reactant is supplied to the reaction chamber while the second reactant is not.
摘要翻译：通过化学气相沉积沉积具有基本均匀厚度的膜的方法，包括：提供反应室; 在所述反应室中提供衬底; 对衬底进行一系列沉积循环，其中每个沉积循环包括以下步骤：（a）在第一时间间隔期间，将第一反应物供应到反应室; （b）在第二时间间隔期间，向所述反应室供应第二反应物; 和（c）在第三时间间隔期间，第一和第二反应物都不向反应室供应; 其中所述第二时间间隔的开始位于所述第一时间间隔内，使得在所述第一时间间隔的开始和所述第二时间间隔的开始之间存在预曝光间隔，在所述预曝光间隔期间，所述第一反应物为供应到反应室，而第二反应物不是。

8. 发明申请

US20060216932A1 Plasma pre-treating surfaces for atomic layer deposition 有权
公开(公告)号：US20060216932A1
公开(公告)日：2006-09-28
申请号：US11359884
申请日：2006-02-21
申请人： Devendra Kumar , Kamal Goundar , Nathanael Kemeling , Hideaki Fukuda , Hessel Sprey , Maarten Stokhof
发明人： Devendra Kumar , Kamal Goundar , Nathanael Kemeling , Hideaki Fukuda , Hessel Sprey , Maarten Stokhof
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/02063 , C23C14/02 , C23C16/02 , C23C16/36 , C23C16/45525 , C23C16/45531 , H01L21/28562 , H01L21/3105 , H01L21/76807 , H01L21/7681 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76873
摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed in, preferably, insulating layers. The layers are then adequately treated with a particular plasma process. Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction can occur without significantly filling the pores forming improved interconnects.

9. 发明授权

US07498242B2 Plasma pre-treating surfaces for atomic layer deposition 有权
标题翻译：用于原子层沉积的等离子体预处理表面
公开(公告)号：US07498242B2
公开(公告)日：2009-03-03
申请号：US11359884
申请日：2006-02-21
申请人： Devendra Kumar , Kamal Kishore Goundar , Nathanael R. C. Kemeling , Hideaki Fukuda , Hessel Sprey , Maarten Stokhof
发明人： Devendra Kumar , Kamal Kishore Goundar , Nathanael R. C. Kemeling , Hideaki Fukuda , Hessel Sprey , Maarten Stokhof
IPC分类号： H01L21/322
CPC分类号： H01L21/02063 , C23C14/02 , C23C16/02 , C23C16/36 , C23C16/45525 , C23C16/45531 , H01L21/28562 , H01L21/3105 , H01L21/76807 , H01L21/7681 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76873
摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed in, preferably, insulating layers. The layers are then adequately treated with a particular plasma process. Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction can occur without significantly filling the pores forming improved interconnects.
摘要翻译：提供了集成电路中双镶嵌结构的保形衬里的方法和结构。优选实施例涉及在多孔材料中形成的开口上提供适形衬里。沟槽形成在，优选绝缘层中。然后用特定的等离子体工艺充分处理各层。在这种等离子体处理之后，可以发生自限制的自饱和原子层沉积（ALD）反应，而不显着填充形成改进的互连的孔。

10. 发明授权

US08652573B2 Method of CVD-depositing a film having a substantially uniform film thickness 有权
标题翻译： CVD沉积膜厚度基本均匀的膜的方法
公开(公告)号：US08652573B2
公开(公告)日：2014-02-18
申请号：US13183016
申请日：2011-07-14
申请人： Maarten Stokhof , Hessel Sprey , Tatsuya Yoshimi , Bert Jongbloed , Noureddine Adjeroud
发明人： Maarten Stokhof , Hessel Sprey , Tatsuya Yoshimi , Bert Jongbloed , Noureddine Adjeroud
IPC分类号： C23C16/00 , C23C16/08
CPC分类号： C23C16/34 , C23C16/45523
摘要： Method of depositing a film having a substantially uniform thickness by means of chemical vapor deposition, comprising: providing a reaction chamber; providing a substrate in said reaction chamber; subjecting the substrate to a series of deposition cycles, wherein each deposition cycle includes the steps of: (a) during a first time interval, supplying a first reactant to the reaction chamber; (b) during a second time interval, supplying a second reactant to the reaction chamber; and (c) during a third time interval, supplying neither the first nor the second reactant to the reaction chamber; wherein a start of the second time interval lies within the first time interval, such that a pre-exposure interval exists between a start of the first time interval and the start of the second time interval, during which pre-exposure interval the first reactant is supplied to the reaction chamber while the second reactant is not.
摘要翻译：通过化学气相沉积沉积具有基本均匀厚度的膜的方法，包括：提供反应室; 在所述反应室中提供衬底; 对衬底进行一系列沉积循环，其中每个沉积循环包括以下步骤：（a）在第一时间间隔期间，向反应室供应第一反应物; （b）在第二时间间隔期间，向所述反应室供应第二反应物; 和（c）在第三时间间隔期间，第一和第二反应物都不向反应室供应; 其中所述第二时间间隔的开始位于所述第一时间间隔内，使得在所述第一时间间隔的开始和所述第二时间间隔的开始之间存在预曝光间隔，在所述预曝光间隔期间，所述第一反应物为供应到反应室，而第二反应物不是。

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