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1. 发明申请

US20060120148A1 Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储单元的方法
公开(公告)号：US20060120148A1
公开(公告)日：2006-06-08
申请号：US11238381
申请日：2005-09-29
申请人： Sung-Min Kim , Eun-Jung Yun , Jong-Soo Seo , Du-Eung Kim , Beak-Hyung Cho , Byung-Seo Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Jong-Soo Seo , Du-Eung Kim , Beak-Hyung Cho , Byung-Seo Kim
IPC分类号： G11C11/00
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79
摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

2. 发明申请

US20120161247A1 Gate-All-Around Integrated Circuit Devices and Methods of Manufacturing the Same 有权
标题翻译： Gate-All-Around集成电路器件及其制造方法
公开(公告)号：US20120161247A1
公开(公告)日：2012-06-28
申请号：US13411699
申请日：2012-03-05
申请人： Eun-Jung Yun , Sung-yung Lee , Min-sang Kim , Sung-min Kim
发明人： Eun-Jung Yun , Sung-yung Lee , Min-sang Kim , Sung-min Kim
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392
摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.
摘要翻译：栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。第一和第二源极/漏极区域与有源区域形成p-n整流结。沟道区域在第一和第二源极/漏极区域之间延伸。绝缘栅极围绕通道区域。

3. 发明授权

US08198704B2 Semiconductor device including a crystal semiconductor layer 有权
标题翻译：包括晶体半导体层的半导体器件
公开(公告)号：US08198704B2
公开(公告)日：2012-06-12
申请号：US12710378
申请日：2010-02-23
申请人： Sung-Min Kim , Eun-Jung Yun
发明人： Sung-Min Kim , Eun-Jung Yun
IPC分类号： H01L29/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/02667 , H01L21/02639 , H01L21/2026 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.
摘要翻译：在一个实施例中，制造具有晶体半导体层的半导体器件的方法包括制备半导体衬底并在半导体衬底上形成预活性图案。预活性图案包括阻挡图案和非单晶半导体图案。牺牲非单晶半导体层覆盖预活性图案和半导体衬底。通过使牺牲非单晶半导体层和非单晶半导体图案结晶，使用半导体衬底作为晶种层，将牺牲非单晶半导体层和非单晶半导体图案改变为牺牲晶体半导体层和晶体半导体图案。晶体半导体图案和势垒图案构成活性图案。去除牺牲晶体半导体层。

4. 发明授权

US07897463B2 Methods of fabricating vertical twin-channel transistors 失效
标题翻译：制造垂直双通道晶体管的方法
公开(公告)号：US07897463B2
公开(公告)日：2011-03-01
申请号：US12651688
申请日：2010-01-04
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

5. 发明授权

US07768070B2 Semiconductor devices having field effect transistors 有权
标题翻译：具有场效应晶体管的半导体器件
公开(公告)号：US07768070B2
公开(公告)日：2010-08-03
申请号：US11832589
申请日：2007-08-01
申请人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
发明人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.
摘要翻译：一种具有场效应晶体管的半导体器件及其制造方法。通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。原位掺杂的外延图案贯穿整个杂质浓度。因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

6. 发明授权

US07723762B2 Schottky barrier FinFET device and fabrication method thereof 有权
标题翻译：肖特基势垒FinFET器件及其制造方法
公开(公告)号：US07723762B2
公开(公告)日：2010-05-25
申请号：US11598374
申请日：2006-11-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

7. 发明申请

US20080087941A1 Nonvolatile Memory Devices Having Stacked Structures and Methods of Fabricating the Same 有权
标题翻译：具有堆叠结构的非易失性存储器件及其制造方法
公开(公告)号：US20080087941A1
公开(公告)日：2008-04-17
申请号：US11668115
申请日：2007-01-29
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Kyoung-Hwan Yeo
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7851 , H01L29/78648 , H01L29/78696 , H01L29/7926
摘要： A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.
摘要翻译：存储器件包括衬底上的第一有源区和衬底上的第一和第二源极/漏极区，邻接第一有源区的相应的第一和第二侧壁。第一栅极结构设置在第一和第二源/漏区之间的第一有源区上。第二有源区域设置在第一栅极结构之间并邻接第一和第二源极/漏极区域。第二栅极结构设置在覆盖第一栅极结构的第二有源区上。

8. 发明申请

US20080081442A1 Methods of forming a pattern and methods of manufacturing a memory device using the same 有权
标题翻译：形成图案的方法和使用该图案的存储器件的制造方法
公开(公告)号：US20080081442A1
公开(公告)日：2008-04-03
申请号：US11605266
申请日：2006-11-29
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/02381 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L21/28282 , H01L27/11568 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： In a method of forming a pattern, a sacrificial layer pattern and a stop layer pattern for preventing or reducing an epitaxial growth may be formed on a substrate. The sacrificial layer pattern may have a first hole therethrough, and the first hole partially exposes a top surface of the substrate. At least one active pattern may be formed on a bottom and a sidewall of the first hole by performing a selective epitaxial growth process on the top surface of the substrate and a sidewall of the sacrificial layer pattern. The sacrificial layer pattern and the stop layer pattern for preventing or reducing the epitaxial growth may be removed from the substrate. The at least one active pattern formed by the above method may have a finer size and an improved shaped compared to a conventional active pattern formed by directly patterning layers using a photoresist pattern. Damages in a photolithography process may be prevented or reduced from being generated.
摘要翻译：在形成图案的方法中，可以在基板上形成用于防止或减少外延生长的牺牲层图案和停止层图案。牺牲层图案可以具有穿过其的第一孔，并且第一孔部分地暴露衬底的顶表面。通过在衬底的顶表面和牺牲层图案的侧壁上执行选择性外延生长工艺，可以在第一孔的底部和侧壁上形成至少一个活性图案。可以从衬底去除用于防止或减少外延生长的牺牲层图案和停止层图案。与通过使用光致抗蚀剂图案直接图案化图案形成的常规有源图案相比，通过上述方法形成的至少一个有源图案可以具有更细的尺寸和改进的形状。可以防止或减少光刻工艺中的损伤。

9. 发明申请

US20060289907A1 Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions and methods of fabricating the same 失效
标题翻译：具有低于源区和漏区的缓冲区的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US20060289907A1
公开(公告)日：2006-12-28
申请号：US11513474
申请日：2006-08-31
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

10. 发明申请

US20050158934A1 Semiconductor devices having field effect transistors and methods of fabricating the same 有权
标题翻译：具有场效应晶体管的半导体器件及其制造方法
公开(公告)号：US20050158934A1
公开(公告)日：2005-07-21
申请号：US11030770
申请日：2005-01-05
申请人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
发明人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/786 , H01L21/425
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.
摘要翻译：一种具有场效应晶体管的半导体器件及其制造方法。通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。原位掺杂的外延图案贯穿整个杂质浓度。因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

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