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1. 发明授权

US07541645B2 Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions 失效
标题翻译：金属氧化物半导体（MOS）晶体管具有低于源极和漏极区域的缓冲区域
公开(公告)号：US07541645B2
公开(公告)日：2009-06-02
申请号：US11513474
申请日：2006-08-31
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L29/76
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

2. 发明申请

US20060289907A1 Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions and methods of fabricating the same 失效
标题翻译：具有低于源区和漏区的缓冲区的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US20060289907A1
公开(公告)日：2006-12-28
申请号：US11513474
申请日：2006-08-31
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

3. 发明授权

US07122431B2 Methods of fabrication metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions 有权
标题翻译：制造具有低于源极和漏极区域的缓冲区的金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US07122431B2
公开(公告)日：2006-10-17
申请号：US10754676
申请日：2004-01-09
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/00 , H01L21/20 , H01L21/425
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： Methods of forming a unit cell of a metal oxide semiconductor (MOS) transistor are provided. An integrated circuit substrate is formed. A MOS transistor is formed on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. The first and second spaced apart buffer regions are formed beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：提供了形成金属氧化物半导体（MOS）晶体管的晶胞的方法。形成集成电路基板。在集成电路基板上形成MOS晶体管。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区形成在源极区域和漏极区域之间以及源极区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

4. 发明授权

US07473963B2 Metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管
公开(公告)号：US07473963B2
公开(公告)日：2009-01-06
申请号：US11854734
申请日：2007-09-13
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

5. 发明申请

US20080001218A1 Metal Oxide Semiconductor (MOS) Transistors Having Three Dimensional Channels 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管
公开(公告)号：US20080001218A1
公开(公告)日：2008-01-03
申请号：US11854734
申请日：2007-09-13
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

6. 发明授权

US07285466B2 Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
标题翻译：形成具有三维通道的金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US07285466B2
公开(公告)日：2007-10-23
申请号：US10909471
申请日：2004-08-02
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

7. 发明申请

US20050032322A1 Metal oxide semiconductor (MOS) transistors having three dimensional channels and methods of fabricating the same 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US20050032322A1
公开(公告)日：2005-02-10
申请号：US10909471
申请日：2004-08-02
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/786 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/76 , H01L21/3205
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

8. 发明授权

US06940129B2 Double gate MOS transistors 失效
标题翻译：双栅MOS晶体管
公开(公告)号：US06940129B2
公开(公告)日：2005-09-06
申请号：US10715664
申请日：2003-11-18
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648 , H01L29/78654
摘要： A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.
摘要翻译：双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。半导体柱支撑晶体管有源区，使得晶体管有源区与衬底有源区间隔开。至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。底栅电极与衬底有源区，晶体管有源区和半导体柱绝缘。至少一个顶栅电极跨越晶体管有源区，并且具有与底栅电极的侧壁接触的至少一个端。顶栅电极与底栅电极重叠并与晶体管有源区绝缘。还提供制造这种晶体管的方法。

9. 发明授权

US07615429B2 Methods of fabricating field effect transistors having multiple stacked channels 有权
标题翻译：制造具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US07615429B2
公开(公告)日：2009-11-10
申请号：US11948175
申请日：2007-11-30
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。在预活化图案的相对端处，在衬底上形成源极/漏极区域。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

10. 发明授权

US07397131B2 Self-aligned semiconductor contact structures 失效
标题翻译：自对准半导体接触结构
公开(公告)号：US07397131B2
公开(公告)日：2008-07-08
申请号：US11396819
申请日：2006-04-03
申请人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
发明人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
IPC分类号： H01L29/772
CPC分类号： H01L21/76831 , H01L21/28114 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10888 , H01L27/10894 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.
摘要翻译：自对准接触结构及其形成方法包括具有相邻侧壁的选定的相邻栅电极，其被配置为朝向彼此成角度。可以使用能够延长接触窗口的长度以限定接触窗的侧壁的衬里层来保护栅电极的成角度的表面。

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