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1. 发明申请

US20130020647A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130020647A1
公开(公告)日：2013-01-24
申请号：US13540799
申请日：2012-07-03
申请人： Sung-Min HWANG , In-Wook Oh , Woonkyung Lee , Aaron Park , Hoosung Cho
发明人： Sung-Min HWANG , In-Wook Oh , Woonkyung Lee , Aaron Park , Hoosung Cho
IPC分类号： H01L29/78 , H01L23/498
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/11575
摘要： Semiconductor devices are provided. The semiconductor device includes conductive patterns vertically stacked on a substrate to be spaced apart from each other, and pad patterns electrically connected to respective ones of the conductive patterns. Each of the pad patterns includes a flat portion extending from an end of the conductive pattern in a first direction parallel with the substrate and a landing sidewall portion upwardly extending from an end of the flat portion. A width of a portion of the landing sidewall portion in a second direction parallel with the substrate and perpendicular to the first direction is less than a width of the flat portion in the second direction. The related methods are also provided.
摘要翻译：提供半导体器件。半导体器件包括垂直堆叠在基板上以彼此间隔开的导电图案，以及电连接到相应导电图案的焊盘图案。每个焊盘图案包括从平行于基板的第一方向从导电图案的端部延伸的平坦部分和从平坦部分的端部向上延伸的着陆侧壁部分。着陆侧壁部的与基板平行且垂直于第一方向的第二方向的一部分的宽度小于第二方向上的平坦部的宽度。还提供了相关方法。

2. 发明授权

US08921918B2 Three-dimensional semiconductor devices 有权
标题翻译：三维半导体器件
公开(公告)号：US08921918B2
公开(公告)日：2014-12-30
申请号：US13280759
申请日：2011-10-25
申请人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
发明人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
摘要翻译：可以提供三维半导体器件。这些装置可以包括包括栅极图案和绝缘图案的堆叠结构。堆叠结构还可以包括第一部分和第二部分，并且堆叠结构的第二部分可以具有比第一部分更窄的宽度。装置还可以包括穿透堆叠结构的活动图案。所述装置还可以包括与堆栈结构相邻的公共源区。所述装置还可以包括在公共源区上的捆扎接触塞。

3. 发明申请

US20120098049A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120098049A1
公开(公告)日：2012-04-26
申请号：US13276682
申请日：2011-10-19
申请人： Hui-Chang MOON , Sung-Min Hwang , Woonkyung Lee
发明人： Hui-Chang MOON , Sung-Min Hwang , Woonkyung Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11556 , H01L29/7926
摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
摘要翻译：三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。第一串选择栅极设置在单元栅极的最上面的单元栅极上。每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。第一补充导电图案与第一串选择门之一的侧壁接触。

4. 发明授权

US08729622B2 Three dimensional semiconductor memory devices and methods of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08729622B2
公开(公告)日：2014-05-20
申请号：US13276682
申请日：2011-10-19
申请人： Hui-Chang Moon , Sung-Min Hwang , Woonkyung Lee
发明人： Hui-Chang Moon , Sung-Min Hwang , Woonkyung Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11556 , H01L29/7926
摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
摘要翻译：三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。第一串选择栅极设置在单元栅极的最上面的单元栅极上。每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。第一补充导电图案与第一串选择门之一的侧壁接触。

5. 发明申请

US20120208347A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120208347A1
公开(公告)日：2012-08-16
申请号：US13367792
申请日：2012-02-07
申请人： Sung-Min Hwang , Kwangmin Park , Woonkyung Lee , Jintaek Park , Byong-byun Jang , Jumi Yun
发明人： Sung-Min Hwang , Kwangmin Park , Woonkyung Lee , Jintaek Park , Byong-byun Jang , Jumi Yun
IPC分类号： H01L21/762
CPC分类号： H01L21/762 , H01L21/76224 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating a three-dimensional semiconductor device are provided. Methods may include forming a stack structure including first layers and second layers alternately stacked on a substrate, patterning the stack structure to form at least one isolation trench, forming channel structures penetrating the stack structure and being spaced apart from the isolation trench, and forming upper interconnection lines on the stack structure to connect the channel structures to each other. An isolation trench may be formed prior to formation of the channel structures.
摘要翻译：提供制造三维半导体器件的方法。方法可以包括形成堆叠结构，其包括交替层叠在衬底上的第一层和第二层，图案化堆叠结构以形成至少一个隔离沟槽，形成贯穿堆叠结构并与隔离沟槽间隔开的沟道结构，在堆叠结构上的互连线将通道结构彼此连接。可以在形成通道结构之前形成隔离沟槽。

6. 发明申请

US20150145018A1 Semiconductor Devices 审中-公开
标题翻译：半导体器件
公开(公告)号：US20150145018A1
公开(公告)日：2015-05-28
申请号：US14568737
申请日：2014-12-12
申请人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
发明人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L29/49 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。第一浓度可能高于第二浓度。

7. 发明授权

US08476713B2 Vertical-type semiconductor device and method of manufacturing the same 有权
标题翻译：立式半导体器件及其制造方法
公开(公告)号：US08476713B2
公开(公告)日：2013-07-02
申请号：US12588270
申请日：2009-10-09
申请人： Seung-Jun Lee , Woonkyung Lee
发明人： Seung-Jun Lee , Woonkyung Lee
IPC分类号： H01L21/70 , H01L21/336
CPC分类号： H01L27/11551 , H01L27/11526 , H01L27/11529 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A vertical-type semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other, a semiconductor structure through the wordline structure, a gate dielectric between the wordline structure and the semiconductor structure, and a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure.
摘要翻译：垂直型半导体器件包括具有单元区域和外围电路区域的半导体衬底，半导体衬底的单元区域上的字线结构，该字线结构包括堆叠在彼此顶部的多个字线，半导体结构通过字线结构，字线结构和半导体结构之间的栅极电介质和外围电路区域上的伪字线结构，虚拟字线结构具有垂直结构并且包括与字线结构相同的部件。

8. 发明授权

US08873294B2 Nonvolatile memory devices, erasing methods thereof and memory systems including the same 有权
标题翻译：非易失性存储器件，其擦除方法和包括其的存储器系统
公开(公告)号：US08873294B2
公开(公告)日：2014-10-28
申请号：US13295335
申请日：2011-11-14
申请人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
发明人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
IPC分类号： G11C16/16 , G11C16/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , H01L29/792 , G11C16/30 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.
摘要翻译：提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

9. 发明授权

US08576629B2 Operating method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US08576629B2
公开(公告)日：2013-11-05
申请号：US13315523
申请日：2011-12-09
申请人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线多个第一选择线。

10. 发明申请

US20130182502A1 Operating Methods of Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US20130182502A1
公开(公告)日：2013-07-18
申请号：US13784969
申请日：2013-03-05
申请人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
发明人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
IPC分类号： G11C16/14 , G11C7/14
CPC分类号： G11C16/14 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings; floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。所述方法可以包括将字线擦除电压施加到连接到所述多个单元串的存储单元的字线; 连接到多个单元串的接地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

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