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1. 发明授权

US08507665B2 Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same 有权
标题翻译：用于形成超低介电层的模板衍生物和使用其形成超低介电层的方法
公开(公告)号：US08507665B2
公开(公告)日：2013-08-13
申请号：US13475237
申请日：2012-05-18
申请人： Sung Kyu Min , Ja Chun Ku , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim , Chan Bae Kim
发明人： Sung Kyu Min , Ja Chun Ku , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim , Chan Bae Kim
IPC分类号： C08B37/16
CPC分类号： H01L21/31695 , C08B37/0012 , C08L83/04 , C09D105/16 , C09D183/02 , H01L21/02126 , H01L21/02203 , H01L21/02208 , H01L21/02282 , H01L21/02337
摘要： A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
摘要翻译：使用反应性环糊精衍生物或反应性葡萄糖衍生物作为形成超低介电层的模板衍生物。由反应性环糊精衍生物或用Si-H封端的反应性葡萄糖衍生物形成层，然后在过氧化氢气氛中固化形成超低介电层。

2. 发明授权

US08354350B2 Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same 有权
标题翻译：用于形成超低介电层的模板衍生物和使用其形成超低介电层的方法
公开(公告)号：US08354350B2
公开(公告)日：2013-01-15
申请号：US13475178
申请日：2012-05-18
申请人： Sung Kyu Min , Ja Chun Ku , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim , Chan Bae Kim
发明人： Sung Kyu Min , Ja Chun Ku , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim , Chan Bae Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/31695 , C08B37/0012 , C08L83/04 , C09D105/16 , C09D183/02 , H01L21/02126 , H01L21/02203 , H01L21/02208 , H01L21/02282 , H01L21/02337
摘要： A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
摘要翻译：使用反应性环糊精衍生物或反应性葡萄糖衍生物作为形成超低介电层的模板衍生物。由反应性环糊精衍生物或用Si-H封端的反应性葡萄糖衍生物形成层，然后在过氧化氢气氛中固化形成超低介电层。

3. 发明授权

US08202807B2 Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same 有权
标题翻译：用于形成超低介电层的模板衍生物和使用其形成超低介电层的方法
公开(公告)号：US08202807B2
公开(公告)日：2012-06-19
申请号：US11964950
申请日：2007-12-27
申请人： Sung Kyu Min , Ja Chun Ku , Chan Bae Kim , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim
发明人： Sung Kyu Min , Ja Chun Ku , Chan Bae Kim , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/31695 , C08B37/0012 , C08L83/04 , C09D105/16 , C09D183/02 , H01L21/02126 , H01L21/02203 , H01L21/02208 , H01L21/02282 , H01L21/02337
摘要： A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
摘要翻译：使用反应性环糊精衍生物或反应性葡萄糖衍生物作为形成超低介电层的模板衍生物。由反应性环糊精衍生物或用Si-H封端的反应性葡萄糖衍生物形成层，然后在过氧化氢气氛中固化形成超低介电层。

4. 发明授权

US08530330B2 Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region 有权
标题翻译：一种能够防止活性区域的宽度减小的半导体装置的制造方法
公开(公告)号：US08530330B2
公开(公告)日：2013-09-10
申请号：US12100455
申请日：2008-04-10
申请人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim , Wan Soo Kim
发明人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim , Wan Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76224
摘要： A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.
摘要翻译：描述了可以防止隔离结构的损失并且还可以稳定地形成外延硅层的半导体器件的制造方法。半导体器件的制造方法包括在具有有源区和隔离区的半导体衬底中限定沟槽。沟槽部分地填充有第一绝缘层。在填充有第一绝缘层的沟槽的表面上形成蚀刻保护层。在由蚀刻保护层形成的沟槽中填充第二绝缘层，以在半导体衬底的隔离区域中形成隔离结构。最后，半导体衬底的有源区的部分被凹入，使得隔离结构的高度高于半导体衬底的有源区。

5. 发明授权

US07763523B2 Method for forming device isolation structure of semiconductor device using annealing steps to anneal flowable insulation layer 失效
标题翻译：使用退火步骤对可流动绝缘层进行退火的半导体器件的器件隔离结构的方法
公开(公告)号：US07763523B2
公开(公告)日：2010-07-27
申请号：US12045073
申请日：2008-03-10
申请人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim
发明人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/0206 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02318 , H01L21/02337 , H01L21/3125 , H01L21/316 , H01L21/76227
摘要： A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern.
摘要翻译：提出了使用至少三个退火步骤形成半导体器件的器件隔离结构以退火可流动绝缘层的方法。该方法包括以下步骤：在具有暴露半导体衬底的器件隔离区域的有源区的半导体衬底上形成硬掩模图案; 蚀刻通过硬掩模图案曝光的半导体衬底的器件隔离区，并且其中形成沟槽; 形成可流动的绝缘层以填充沟槽; 首先将可流动绝缘层退火至少三次; 对所述第一退火可流动绝缘层进行第二退火; 去除所述第二退火的可流动绝缘层，直到所述硬掩模图案被暴露; 并去除暴露的硬掩模图案。

6. 发明授权

US08349636B2 Method of manufacturing a phase change memory device using a cross patterning technique 有权
标题翻译：使用交叉图案化技术制造相变存储器件的方法
公开(公告)号：US08349636B2
公开(公告)日：2013-01-08
申请号：US12834141
申请日：2010-07-12
申请人： Jang Uk Lee , Kang Sik Choi , Hae Chan Park , Jin Hyock Kim , Ja Chun Ku
发明人： Jang Uk Lee , Kang Sik Choi , Hae Chan Park , Jin Hyock Kim , Ja Chun Ku
IPC分类号： H01L21/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.
摘要翻译：提供一种制造相变存储器件的方法。在半导体衬底上形成具有以恒定距离隔开的多个金属字线的第一绝缘层。形成具有阻挡金属层，多晶硅层和硬掩模层的多个线结构以覆盖在多个金属字线上。在线路结构之间形成第二绝缘层。通过使用与金属字线交叉的掩模图案蚀刻线结构的硬掩模层和多晶硅层来形成交叉图案。第三绝缘层埋在交叉图案之间的空间内。形成自对准的相变接触孔，同时，通过选择性地去除构成交叉图案的硬掩模层，形成由剩余多晶硅层形成的二极管图案。

7. 发明申请

US20080120514A1 THERMAL MANAGEMENT OF ON-CHIP CACHES THROUGH POWER DENSITY MINIMIZATION 审中-公开
标题翻译：通过功率密度最小化进行片上高速缓存的热管理
公开(公告)号：US20080120514A1
公开(公告)日：2008-05-22
申请号：US11938040
申请日：2007-11-09
申请人： Yehea Ismail , Gokhan Memik , Ja Chun Ku , Serkan Ozdemir
发明人： Yehea Ismail , Gokhan Memik , Ja Chun Ku , Serkan Ozdemir
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/3275 , H01L23/34 , H01L23/42 , H01L2924/0002 , Y02D10/14 , Y02D50/20 , H01L2924/00
摘要： Certain embodiments provide systems and methods for reducing power consumption in on-chip caches. Certain embodiments include Power Density-Minimized Architecture (PMA) and Block Permutation Scheme (BPS) for thermal management of on-chip caches. Instead of turning off entire banks, PMA architecture spreads out active parts in a cache bank by turning off alternating rows in a bank. This reduces the power density of the active parts in the cache, which then lowers the junction temperature. The drop in the temperature results in energy savings from the remaining active parts of the cache. BPS aims to maximize the physical distance between the logically consecutive blocks of the cache. Since there is spatial locality in caches, this distribution results in an increase in the distance between hot spots, thereby reducing the peak temperature. The drop in the peak temperature then results in a leakage power reduction in the cache.
摘要翻译：某些实施例提供用于降低片上高速缓存中的功耗的系统和方法。某些实施例包括用于片上高速缓存的热管理的功率密度最小化架构（PMA）和块置换方案（BPS）。 PMA架构不是关闭整个银行，而是通过关闭银行中的交替行来扩展缓存库中的活动部分。这降低了高速缓存中活动部件的功率密度，从而降低了结温。温度的降低导致缓存的剩余活动部分的能量节省。 BPS旨在最大化缓存的逻辑连续块之间的物理距离。由于缓存中存在空间局部性，所以这种分布导致热点之间的距离增加，从而降低峰值温度。然后，峰值温度的下降导致高速缓存中的泄漏功率降低。

8. 发明申请

US20120153247A1 SEMICONDUCTOR DEVICE HAVING RESISTIVE DEVICE 有权
标题翻译：具有电阻器件的半导体器件
公开(公告)号：US20120153247A1
公开(公告)日：2012-06-21
申请号：US13073521
申请日：2011-03-28
申请人： Seung Beom BAEK , Ja Chun Ku , Young Ho Lee , Jin Hyock Kim
发明人： Seung Beom BAEK , Ja Chun Ku , Young Ho Lee , Jin Hyock Kim
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.
摘要翻译：半导体存储器件包括垂直形成在半导体衬底的表面上的多个字线，其中每对多条字线形成一组字线，平行于半导体衬底的表面形成的位线，多个堆叠在构成所述一组字线的每一对的字线之间，以及设置在所述一个字线组中的所述位线中的相应位线与所述一对字线中的相邻一个之间的单元存储单元。

9. 发明授权

US08344346B2 Semiconductor device having resistive device 有权
标题翻译：具有电阻器件的半导体器件
公开(公告)号：US08344346B2
公开(公告)日：2013-01-01
申请号：US13073521
申请日：2011-03-28
申请人： Seung Beom Baek , Ja Chun Ku , Young Ho Lee , Jin Hyock Kim
发明人： Seung Beom Baek , Ja Chun Ku , Young Ho Lee , Jin Hyock Kim
IPC分类号： H01L29/02 , H01L29/06 , G11C11/00
CPC分类号： H01L27/249 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.
摘要翻译：半导体存储器件包括垂直形成在半导体衬底的表面上的多个字线，其中每对多条字线形成一组字线，平行于半导体衬底的表面形成的位线，多个堆叠在构成所述一组字线的每一对的字线之间，以及设置在所述一个字线组中的所述位线中的相应位线与所述一对字线中的相邻一个之间的单元存储单元。

10. 发明授权

US06316349B1 Method for forming contacts of semiconductor devices 失效
标题翻译：形成半导体器件的触点的方法
公开(公告)号：US06316349B1
公开(公告)日：2001-11-13
申请号：US09438048
申请日：1999-11-10
申请人： Jeong Ho Kim , Jae Ok Ryu , Ja Chun Ku , Jin Woong Kim , Si Bum Kim , Su Jin Oh
发明人： Jeong Ho Kim , Jae Ok Ryu , Ja Chun Ku , Jin Woong Kim , Si Bum Kim , Su Jin Oh
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/3144 , H01L21/76801 , H01L21/76834 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for forming contacts of a semiconductor device. In accordance with the invention, an oxidized silicon-rich nitride film is used as an etch barrier film for a self-aligned contact (SAC) process. Accordingly, the oxidized silicon-rich nitride film exhibits less stress, as compared to an LPCVD nitride film, thereby being capable of avoiding a degradation in the characteristics of the devices finally produced or distortion of the wafer used. There is no formation of cracks occurring in the nitride film during a subsequent thermal process. It is also unnecessary to conduct an additional reflection preventing process. Accordingly, the entire process is simplified. It is also possible to improve a decrease in the operating speed of the devices due to a parasitic capacitance existing among conductive lines because the oxidized silicon-rich nitride film has a low dielectric constant, as compared to nitride films. No damage occurs in the oxidized silicon-rich nitride film, so that it is possible to prevent the substrate from being damaged.
摘要翻译：公开了一种形成半导体器件的接触的方法。根据本发明，氧化富硅氮化物膜用作自对准接触（SAC）工艺的蚀刻阻挡膜。因此，与LPCVD氮化物膜相比，氧化富硅氮化物膜的应力显示较小，从而能够避免最终产生的器件的特性劣化或所使用的晶片的变形。在随后的热处理中，在氮化物膜中不会形成裂缝。也不需要进行附加的防反射处理。因此，整个过程被简化。与氮化膜相比，由于氧化富硅的氮化物膜具有低的介电常数，所以可以改善由于导电线中存在的寄生电容而引起的器件的工作速度的降低。在氧化富硅的氮化物膜中不会发生损伤，从而可以防止衬底损坏。

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