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1. 发明授权

US08679938B2 Shallow trench isolation for device including deep trench capacitors 失效
标题翻译：用于包括深沟槽电容器的器件的浅沟槽隔离
公开(公告)号：US08679938B2
公开(公告)日：2014-03-25
申请号：US13366576
申请日：2012-02-06
申请人： Sunfei Fang , Oleg Gluschenkov , Byeong Y. Kim , Rishikesh Krishnan , Daewon Yang
发明人： Sunfei Fang , Oleg Gluschenkov , Byeong Y. Kim , Rishikesh Krishnan , Daewon Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/10861 , H01L21/76224 , H01L29/66181 , H01L29/945
摘要： A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
摘要翻译：在包括沟槽电容元件的器件的有源区中形成浅沟槽隔离（STI）的方法，包括金属板和高k电介质的沟槽电容元件包括在器件的有源区中蚀刻STI沟槽，其中所述STI沟槽直接邻近所述沟槽电容元件的金属板或高k电介质中的至少一个; 以及在所述STI沟槽中形成氧化物衬垫，其中所述氧化物衬垫选择性地形成到所述金属板或高k电介质，其中形成所述氧化物衬垫在约600℃或更低的温度下进行。

2. 发明授权

US08629017B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08629017B2
公开(公告)日：2014-01-14
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

3. 发明授权

US08227311B2 Method of forming enhanced capacitance trench capacitor 有权
标题翻译：形成增强型电容沟槽电容器的方法
公开(公告)号：US08227311B2
公开(公告)日：2012-07-24
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L21/8242
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

4. 发明授权

US08188528B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08188528B2
公开(公告)日：2012-05-29
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

5. 发明申请

US20120086064A1 METHOD OF FORMING ENHANCED CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：形成增强型电容式电容器的方法
公开(公告)号：US20120086064A1
公开(公告)日：2012-04-12
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

6. 发明授权

US07595232B2 CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors 失效
标题翻译：采用嵌入式连接器的混合定向技术（HOT）的CMOS器件
公开(公告)号：US07595232B2
公开(公告)日：2009-09-29
申请号：US11470819
申请日：2006-09-07
申请人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
发明人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
摘要翻译：本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

7. 发明授权

US06404000B1 Pedestal collar structure for higher charge retention time in trench-type DRAM cells 失效
标题翻译：基座领结构，在沟槽式DRAM单元中具有更高的电荷保留时间
公开(公告)号：US06404000B1
公开(公告)日：2002-06-11
申请号：US09599261
申请日：2000-06-22
申请人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
发明人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
IPC分类号： H01L2972
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.
摘要翻译：一种在衬底中形成有沟槽的存储器结构。环状氧化物位于沟槽的上部，并且包括基座部分。还公开了一种形成具有带衬垫环的环形氧化物的存储器件的方法。

8. 发明授权

US08829585B2 High density memory cells using lateral epitaxy 有权
标题翻译：使用横向外延的高密度记忆细胞
公开(公告)号：US08829585B2
公开(公告)日：2014-09-09
申请号：US13118881
申请日：2011-05-31
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Y. Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Y. Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/92 , H01L27/10829 , H01L27/10861 , H01L27/1203
摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.
摘要翻译：在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

9. 发明授权

US08754446B2 Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material 有权
标题翻译：半导体结构具有由保护性阻挡材料包围的底切栅氧化物栅叠层
公开(公告)号：US08754446B2
公开(公告)日：2014-06-17
申请号：US11468403
申请日：2006-08-30
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

10. 发明申请

US20120171827A1 STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20120171827A1
公开(公告)日：2012-07-05
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

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