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1. 发明授权

US07639056B2 Ultra low area overhead retention flip-flop for power-down applications 有权
标题翻译：用于断电应用的超低面积开销保持触发器
公开(公告)号：US07639056B2
公开(公告)日：2009-12-29
申请号：US11138788
申请日：2005-05-26
申请人： Sumanth Katte Gururajarao , Hugh T. Mair , David B. Scott , Uming Ko
发明人： Sumanth Katte Gururajarao , Hugh T. Mair , David B. Scott , Uming Ko
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , H04W52/0283 , Y02D70/122
摘要： In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.
摘要翻译：在用于数据保持的方法和系统中，数据输入由第一锁存器锁存。耦合到第一锁存器的第二锁存器接收用于保持的数据输入，而在备用电源模式下第一锁存器不工作。第一个锁存器在待机电源模式期间从关闭的第一电源线接收电力。第二锁存器从第二电源线接收电力。控制器接收时钟输入和保持信号，并向第一锁存器和第二锁存器提供时钟输出。保持信号的改变表示转变到待机功率模式。控制器继续将时钟输出保持在预定的电压电平，并且第二锁存器在待机功率模式下继续从第二电源线接收电力，从而保留数据输入。

2. 发明授权

US07282905B2 System and method for IDDQ measurement in system on a chip (SOC) design 有权
标题翻译：系统芯片（SOC）设计中IDDQ测量的系统和方法
公开(公告)号：US07282905B2
公开(公告)日：2007-10-16
申请号：US11010135
申请日：2004-12-10
申请人： Wei Chen , Hugh T. Mair , Uming Ko , David B. Scott
发明人： Wei Chen , Hugh T. Mair , Uming Ko , David B. Scott
IPC分类号： G01R31/26
CPC分类号： G01R31/3008 , G01R31/3012
摘要： System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.
摘要翻译：通过测量IDDQ来检测大型集成电路中的晶体管故障的系统和方法。优选实施例包括由多个选择性地将电源子域耦合到电源引脚的多个主开关（例如主开关410）构成的集成电路的开关结构，多个pi开关（例如，开关415）选择性地耦合功率子域对，以及选择性地将功率子域耦合到VIDDQ引脚的多个IDDQ开关（例如IDDQ开关425）。 pi开关可以对功率子域进行去耦，而IDDQ开关可以测量电源子域中的静态电流。 pi开关和IDDQ开关的使用可以允许测量电源子域中的静态电流，而不需要使用隔离缓冲器，并且需要在不同功率子域中的电流测量之间为集成电路供电和关断。

3. 发明授权

US06989702B2 Retention register with normal functionality independent of retention power supply 有权
标题翻译：保持寄存器具有正常功能，独立于保持电源
公开(公告)号：US06989702B2
公开(公告)日：2006-01-24
申请号：US10613271
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , G11C14/00
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1–M3; M1–M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的阳极（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

4. 发明授权

US07164291B2 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors 有权
标题翻译：具有低泄漏PMOS和高泄漏NMOS晶体管的集成标头开关
公开(公告)号：US07164291B2
公开(公告)日：2007-01-16
申请号：US10916135
申请日：2004-08-11
申请人： Hugh T. Mair , David B. Scott , Rolf Lagerquist
发明人： Hugh T. Mair , David B. Scott , Rolf Lagerquist
IPC分类号： H03K19/0175 , G05F1/10
CPC分类号： H03K17/6872 , H03K19/0013 , H03K19/00315 , H03K2217/0036
摘要： System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
摘要翻译：为集成电路中的电路提供大的导通电流和小的截止电流的系统和方法。优选实施例包括用于向由PMOS晶体管和并联的NMOS晶体管制成的集成电路中的电路提供功率的开关。每个晶体管的栅极端子耦合到单独的控制信号线。 PMOS晶体管以高电压电源电平向电路提供电流，而NMOS晶体管以低电压电源电平向电路提供电流，其中可以在设计期间改变PMOS和NMOS晶体管的尺寸以满足功率需求。根据功率要求，可以使用多个PMOS和NMOS晶体管。 PMOS和NMOS晶体管的组合允许使用有限的制造工艺，其中可以限制晶体管宽度。

5. 发明授权

US07091766B2 Retention register for system-transparent state retention 有权
标题翻译：保留注册表，用于系统透明状态保留
公开(公告)号：US07091766B2
公开(公告)日：2006-08-15
申请号：US10616207
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
IPC分类号： H03K3/12 , H03K3/37 , H03K3/286 , H03K3/356
CPC分类号： H03K3/356008
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的节点（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

6. 发明申请

US20110041592A1 METHODS AND APPARATUSES FOR COMFORT/SUPPORT ANALYSIS OF A SLEEP SUPPORT MEMBER 有权
标题翻译：休闲支持会员舒适/支持分析的方法和设备
公开(公告)号：US20110041592A1
公开(公告)日：2011-02-24
申请号：US12920307
申请日：2008-11-14
申请人： Joe W. Schmoeller , David B. Scott , Robert D. Oexman , Joshua Carrier
发明人： Joe W. Schmoeller , David B. Scott , Robert D. Oexman , Joshua Carrier
IPC分类号： G01N3/40
CPC分类号： A47C31/123 , G01M99/001
摘要： A method of testing a sleep support member, the method including: identifying the sleep support member; determining a tested comfort/support value for the identified sleep support member before the identified sleep support member is provided to a customer; and determining whether the tested comfort/support value is within a predetermined tolerance level of a goal comfort/support value for the identified sleep support member. An apparatus for testing a sleep support member, the apparatus including: an identification unit configured to identify the sleep support member; a comfort/support testing unit configured to determine a tested comfort/support value for the identified sleep support member before the identified sleep support member is provided to a customer; and an analysis unit configured to determine whether the tested comfort/support value is within a predetermined tolerance level of a goal comfort/support value for the identified sleep support member.
摘要翻译：一种测试睡眠支撑构件的方法，所述方法包括：识别所述睡眠支撑构件; 在所识别的睡眠支持构件被提供给顾客之前，确定所识别的睡眠支持构件的测试舒适度/支持值; 以及确定测试的舒适度/支持值是否在所识别的睡眠支持构件的目标舒适度/支持值的预定公差水平内。一种用于测试睡眠支撑构件的装置，所述装置包括：识别单元，被配置为识别所述睡眠支撑构件; 舒适/支持测试单元，其被配置为在所识别的睡眠支持构件被提供给顾客之前确定所识别的睡眠支撑构件的测试舒适度/支持值; 以及分析单元，其被配置为确定所测试的舒适度/支持值是否在所识别的睡眠支持构件的目标舒适度/支持值的预定公差水平内。

7. 发明授权

US07376038B2 Fast access memory architecture 有权
标题翻译：快速访问内存架构
公开(公告)号：US07376038B2
公开(公告)日：2008-05-20
申请号：US11385151
申请日：2006-03-21
申请人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
发明人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
IPC分类号： G11C5/14
CPC分类号： G11C8/10
摘要： A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.
摘要翻译：一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。控制逻辑向存储器提供目标位单元的地址。在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

8. 发明授权

US07307471B2 Adaptive voltage control and body bias for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制和体偏置
公开(公告)号：US07307471B2
公开(公告)日：2007-12-11
申请号：US11213477
申请日：2005-08-26
申请人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
发明人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
IPC分类号： G05F1/565
CPC分类号： H03K19/0008 , H03K19/00384
摘要： A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.
摘要翻译：一种用于自适应地控制提供给设备附近的电路的电压的装置，包括耦合到处理模块的处理模块和第一跟踪元件。第一跟踪元件产生指示与电路相关联的第一估计速度的第一值。该装置还包括耦合到处理模块的第二跟踪元件。第二跟踪元件产生指示与电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与各自的目标值进行比较，并且基于比较使得电压输出被调整。第一和第二跟踪元件包括多个晶体管，至少一些晶体管选择性地提供晶体管偏置电压以调整晶体管速度。

9. 发明授权

US06831337B2 Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (“ESD”) protection 有权
标题翻译：具有不同电阻的晶体管电路轻掺杂扩散区用于静电放电（“ESD”）保护
公开(公告)号：US06831337B2
公开(公告)日：2004-12-14
申请号：US10622052
申请日：2003-07-17
申请人： Zhiqiang Wu , David B. Scott
发明人： Zhiqiang Wu , David B. Scott
IPC分类号： H01L2972
CPC分类号： H01L29/66659 , H01L27/0266 , H01L29/0692 , H01L29/7835
摘要： A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.
摘要翻译：一种在半导体有源区（78）中形成晶体管（70）的方法。该方法形成与半导体有源区域固定关系的栅极结构（G2），从而限定与第一栅极结构侧壁相邻的第一源极/漏极区域（R1）和邻近第二侧壁栅极的第二源极/漏极区域（R2）结构体。该方法还形成在第一源极/漏极区域中形成并在栅极结构下方延伸的轻掺杂扩散区域（801），其中轻掺杂扩散区域包括与栅极结构平行的方向上的变化的电阻。

10. 发明授权

US06249452B1 Semiconductor device having offset twisted bit lines 有权
标题翻译：具有偏移扭转位线的半导体器件
公开(公告)号：US06249452B1
公开(公告)日：2001-06-19
申请号：US09400694
申请日：1999-09-22
申请人： David B. Scott
发明人： David B. Scott
IPC分类号： G11C508
CPC分类号： G11C7/18 , G03F7/2022 , H01L23/528 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A compact data line arrangement (600) includes “twisted” data line pairs (604a-604c) disposed in a first direction. Each twisted data line pair (604a-604c) includes an upper segment pair (608a-608f) that is connected to a lower segment pair (610a-610f) by a twist structure (612a-612c). The upper and lower segment pairs (608a-608f and 610a-610f) can be formed with a first pitch using phase-shifted lithography. The twist structures (612a-612c) are formed from a second conductive layer, and have a greater pitch than the first pitch. The twist structures (612a-612c) are generally arranged in a second direction that is perpendicular to the first direction. Selected twist structures (612b) are offset in the first direction with respect to adjacent twist structures (612a and 612c). The offset twist structures (612a-612c) allow supplemental conductive lines (618) to be formed from the first conductive layer that extend in the first direction, between adjacent offset twist structures (612a and 612b).
摘要翻译：紧凑型数据线装置（600）包括沿第一方向设置的“扭曲”数据线对（604a-604c）。每个扭绞数据线对（604a-604c）包括通过扭曲结构（612a-612c）连接到下部段对（610a-610f）的上段对（608a-608f）。上段和下段对（608a-608f和610a-610f）可以使用相移光刻形成具有第一间距。扭转结构（612a-612c）由第二导电层形成，并且具有比第一间距更大的间距。扭转结构（612a-612c）通常沿垂直于第一方向的第二方向布置。选定的扭转结构（612b）相对于相邻的扭转结构（612a和612c）沿第一方向偏移。偏移扭转结构（612a-612c）允许在相邻的偏移扭曲结构（612a和612b）之间从在第一方向上延伸的第一导电层形成补充导线（618）。

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