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1. 发明授权

US07164291B2 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors 有权
标题翻译：具有低泄漏PMOS和高泄漏NMOS晶体管的集成标头开关
公开(公告)号：US07164291B2
公开(公告)日：2007-01-16
申请号：US10916135
申请日：2004-08-11
申请人： Hugh T. Mair , David B. Scott , Rolf Lagerquist
发明人： Hugh T. Mair , David B. Scott , Rolf Lagerquist
IPC分类号： H03K19/0175 , G05F1/10
CPC分类号： H03K17/6872 , H03K19/0013 , H03K19/00315 , H03K2217/0036
摘要： System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
摘要翻译：为集成电路中的电路提供大的导通电流和小的截止电流的系统和方法。优选实施例包括用于向由PMOS晶体管和并联的NMOS晶体管制成的集成电路中的电路提供功率的开关。每个晶体管的栅极端子耦合到单独的控制信号线。 PMOS晶体管以高电压电源电平向电路提供电流，而NMOS晶体管以低电压电源电平向电路提供电流，其中可以在设计期间改变PMOS和NMOS晶体管的尺寸以满足功率需求。根据功率要求，可以使用多个PMOS和NMOS晶体管。 PMOS和NMOS晶体管的组合允许使用有限的制造工艺，其中可以限制晶体管宽度。

2. 发明授权

US07142019B2 System and method for reducing power-on transient current magnitude 有权
标题翻译：降低上电瞬态电流幅度的系统和方法
公开(公告)号：US07142019B2
公开(公告)日：2006-11-28
申请号：US10933550
申请日：2004-09-03
申请人： Hugh T. Mair , Rolf Lagerquist
发明人： Hugh T. Mair , Rolf Lagerquist
IPC分类号： H03K19/096
CPC分类号： H03K17/164
摘要： System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
摘要翻译：用于降低分布式报头交换机上的上电瞬态电流幅度的系统和方法。优选实施例包括将电路耦合到电源的分布式头部开关，分配的头部开关包括线性顺序的组合开关，每个组合开关包含预充电开关和头部开关。一次通过涉及顺序打开每个预充电开关，这使得分配的标头开关处的电压电平接近最终电压电平的电压电平，而第二次通过涉及顺序地接通每个标头开关。由于分布式标题开关处的电压电平接近最终的电压电平，所以产生的瞬态电流的幅度很小。

3. 发明申请

US20120060138A1 Method and System for Adaptive Physical Design 有权
标题翻译：自适应物理设计方法与系统
公开(公告)号：US20120060138A1
公开(公告)日：2012-03-08
申请号：US12876138
申请日：2010-09-05
申请人： Nitin Kumar Singh , Rajarshee P. Bharadwaj , Rolf Lagerquist , Alice Wang
发明人： Nitin Kumar Singh , Rajarshee P. Bharadwaj , Rolf Lagerquist , Alice Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02
摘要： A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains.
摘要翻译：提供了一种方法，其包括执行包括多个功率域的系统设计的自由放置，其中所述功率域不被约束到物理区域，基于所述功率域中的单元的自由放置来为每个功率域分配物理区域功率域，执行具有每个功率域的系统设计的软集群布置以及被定义为软集群的相应物理区域，基于所述软集群布置来改进至少一个物理区域，基于所述软集群布置重新定义至少一个电源域中的小区，基于单元的软集群放置和相应的物理区域，以及执行与每个功率域的系统设计的硬集群放置以及被定义为硬集群的对应的物理区域以产生最终的电力域。

4. 发明授权

US6011415A Shock sensor circuitry and method for amplifying an input signal including leakage currents 失效
标题翻译：用于放大包括漏电流的输入信号的冲击传感器电路和方法
公开(公告)号：US6011415A
公开(公告)日：2000-01-04
申请号：US919992
申请日：1997-08-28
申请人： Dennis V. Hahn , Rolf Lagerquist , William R. Krenik
发明人： Dennis V. Hahn , Rolf Lagerquist , William R. Krenik
IPC分类号： G11B5/55 , G11B5/596 , G11B19/04 , H01H35/14 , H03F3/04
CPC分类号： G11B5/5582 , G11B19/04 , G11B5/596
摘要： A shock sensor circuitry (26) is provided for processing an input signal generated by a shock sensor (28) in response to the shock sensor (28) detecting a force or shock. The shock sensor circuitry (26) includes a leakage tolerant input amplifier (38) for receiving the input signal, and any leakage currents that may also be provided, and amplifying the input signal to generate an amplified input signal. The leakage tolerant input amplifier (38) provides an ac gain of ten and a dc gain of zero. The shock sensor circuitry (26) also includes a filter and amplification circuit and a window comparator. The filter and amplification circuit filters the amplified input signal and amplifies select frequencies of the amplified input signal to generate a summed signal that is provided to the window comparator and compared to a reference value. The window comparator includes an upper comparator (58), a lower comparator (60), and an output circuit (62) to generate a shock sensor circuitry output signal that indicates whether a shock or force was received at a magnitude greater than the reference value.
摘要翻译：提供冲击传感器电路（26），用于响应于检测到力或冲击的冲击传感器（28）来处理由冲击传感器（28）产生的输入信号。冲击传感器电路（26）包括用于接收输入信号的漏电容量输入放大器（38）以及也可以提供的任何泄漏电流，并放大输入信号以产生放大的输入信号。漏电容量输入放大器（38）提供10的交流增益和零的直流增益。冲击传感器电路（26）还包括滤波器和放大电路以及窗口比较器。滤波器和放大电路对放大的输入信号进行滤波并放大放大的输入信号的选择频率，以产生提供给窗口比较器并与参考值进行比较的求和信号。窗口比较器包括上比较器（58），下比较器（60）和输出电路（62），以产生震动传感器电路输出信号，该信号指示以大于参考值的幅度接收到冲击或力。

5. 发明授权

US10275010B2 Fast and Autonomous mechanism for CPU OC protection 有权
公开(公告)号：US10275010B2
公开(公告)日：2019-04-30
申请号：US15119731
申请日：2015-02-16
申请人： MediaTek Singapore Pte. Ltd. , Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32 , G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

6. 发明申请

US20170068296A1 Fast and Autonomous Mechanism for CPU OC Protection 审中-公开
标题翻译：快速自主的CPU OC保护机制
公开(公告)号：US20170068296A1
公开(公告)日：2017-03-09
申请号：US15119731
申请日：2015-02-16
申请人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist , MediaTek Singapore Pte. Ltd.
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
摘要翻译：提供了一种检测和防止过电流引起的系统故障的方法。 OC保护控制器根据接收到的CPU活动信息监视CPU总功耗。响应监视，如果CPU功耗超过阈值，则OC保护控制器输出频率抖动控制信号，以降低CPU时钟频率，使CPU不达到OC限制。 OC保护控制器还输出PLL频率控制信号，以减少PLL时钟频率，提高系统效率。

7. 发明申请

US20070290270A1 Performance and Area Scalable Cell Architecture Technology 有权
标题翻译：性能和面积可扩展单元架构技术
公开(公告)号：US20070290270A1
公开(公告)日：2007-12-20
申请号：US11745250
申请日：2007-05-07
申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
发明人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
IPC分类号： H01L29/768 , G06F17/50
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11807
摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要翻译：集成电路。集成电路包括具有排列成行的布局的区域。每行可由一对行边界定义。集成电路还包括多个单元，包括第一组单元。第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管。

8. 发明授权

US07633314B2 System and method for reducing power-on-transient current magnitude 有权
标题翻译：用于降低功率瞬态电流幅度的系统和方法
公开(公告)号：US07633314B2
公开(公告)日：2009-12-15
申请号：US11563868
申请日：2006-11-28
申请人： Hugh Mair , Rolf Lagerquist
发明人： Hugh Mair , Rolf Lagerquist
IPC分类号： H03K19/096
CPC分类号： H03K17/164
摘要： System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
摘要翻译：用于降低分布式报头交换机上的上电瞬态电流幅度的系统和方法。优选实施例包括将电路耦合到电源的分布式头部开关，分配的头部开关包括线性顺序的组合开关，每个组合开关包含预充电开关和头部开关。一次通过涉及顺序打开每个预充电开关，这使得分配的标头开关处的电压电平接近最终电压电平的电压电平，而第二次通过涉及顺序地接通每个标头开关。由于分布式标题开关处的电压电平接近最终的电压电平，所以产生的瞬态电流的幅度很小。

9. 发明授权

US07564077B2 Performance and area scalable cell architecture technology 有权
标题翻译：性能和面积可扩展单元架构技术
公开(公告)号：US07564077B2
公开(公告)日：2009-07-21
申请号：US11745250
申请日：2007-05-07
申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
发明人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11807
摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要翻译：集成电路。集成电路包括具有排列成行的布局的区域。每行可由一对行边界定义。集成电路还包括多个单元，包括第一组单元。第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管。

10. 发明授权

US06570415B2 Reduced voltage swing digital differential driver 有权
公开(公告)号：US06570415B2
公开(公告)日：2003-05-27
申请号：US10158659
申请日：2002-05-30
申请人： Hao Chen , Rolf Lagerquist , Hugh Mair
发明人： Hao Chen , Rolf Lagerquist , Hugh Mair
IPC分类号： H03B100
CPC分类号： H04L25/0272 , H03K17/04106 , H03K17/04123 , H03K19/0013 , H03K2217/0036 , H04L25/028
摘要： A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

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