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1. 发明申请

US20130087852A1 EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES 审中-公开
标题翻译：功率半导体器件的边缘终止结构
公开(公告)号：US20130087852A1
公开(公告)日：2013-04-11
申请号：US13267712
申请日：2011-10-06
申请人： Suku Kim , Joseph Andrew Yedinak , Ihsiu Ho
发明人： Suku Kim , Joseph Andrew Yedinak , Ihsiu Ho
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： Edge termination structures for power semiconductor devices and methods for making such structures are described. The power semiconductor devices (or power devices) contain a substrate with an epitaxial layer thereon, an array of substantially-parallel, active trenches formed in the epitaxial layer, with the active trenches containing a transistor structure with an insulated gate conducting layer, a superjunction or shielded region adjacent the active trenches; a peripheral trench surrounding the active trenches, and a source contact area within an upper surface of the epitaxial layer, where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench. Such a configuration allows the edge termination structure to be used with a wide range of breakdown voltages in power MOSFET devices containing PN superjunction structures. Other embodiments are described.
摘要翻译：描述用于功率半导体器件的边缘终端结构及其制造方法。功率半导体器件（或功率器件）包含其上具有外延层的衬底，形成在外延层中的基本上平行的有源沟槽的阵列，其中有源沟槽包含具有绝缘栅极导电层的晶体管结构，超级结或与有源沟槽相邻的屏蔽区域; 围绕有源沟槽的外围沟槽，以及在外延层的上表面内的源极接触区域，其中栅极导电层在超结或屏蔽区域上延伸并在周围的周边沟槽上方延伸。这种配置允许边缘终端结构在包含PN超结构结构的功率MOSFET器件中与宽范围的击穿电压一起使用。描述其他实施例。

2. 发明申请

US20100308402A1 3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的3D通道架构
公开(公告)号：US20100308402A1
公开(公告)日：2010-12-09
申请号：US12480065
申请日：2009-06-08
申请人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
发明人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

3. 发明申请

US20100123225A1 Semiconductor Die Structures for Wafer-Level Chipscale Packaging of Power Devices, Packages and Systems for Using the Same, and Methods of Making the Same 失效
标题翻译：用于晶圆级芯片尺寸的半导体晶片结构，功率器件，封装及其使用系统及其制作方法
公开(公告)号：US20100123225A1
公开(公告)日：2010-05-20
申请号：US12275086
申请日：2008-11-20
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

4. 发明授权

US08058732B2 Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same 失效
标题翻译：用于晶圆级芯片尺寸封装的半导体晶片结构，用于使用它们的功率器件，封装和系统及其制造方法
公开(公告)号：US08058732B2
公开(公告)日：2011-11-15
申请号：US12275086
申请日：2008-11-20
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
IPC分类号： H01L23/48
CPC分类号： H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

5. 发明授权

US08072027B2 3D channel architecture for semiconductor devices 有权
标题翻译：半导体器件的3D通道架构
公开(公告)号：US08072027B2
公开(公告)日：2011-12-06
申请号：US12480065
申请日：2009-06-08
申请人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
发明人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

6. 发明授权

US08624393B2 Methods and designs for localized wafer thinning 有权
标题翻译：局部晶片薄化的方法和设计
公开(公告)号：US08624393B2
公开(公告)日：2014-01-07
申请号：US13404317
申请日：2012-02-24
申请人： Suku Kim , James Murphy , Matthew Reynolds , Romel Manatad , Jan Mancelita , Michael Gruenhagen
发明人： Suku Kim , James Murphy , Matthew Reynolds , Romel Manatad , Jan Mancelita , Michael Gruenhagen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/74 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05 , H01L2224/16 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
摘要翻译：描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。双向图案设计保持通道不与晶片的晶体取向对齐。然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。还描述了其它实施例。

7. 发明授权

US08598035B2 Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same 有权
标题翻译：具有填充弹性材料的后侧沟槽的半导体裸片，用于改善附着，使用其的封装及其制造方法
公开(公告)号：US08598035B2
公开(公告)日：2013-12-03
申请号：US13151495
申请日：2011-06-02
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L21/44
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

8. 发明申请

US20120168947A1 Methods and Designs for Localized Wafer Thinning 有权
标题翻译：局部晶圆薄化的方法与设计
公开(公告)号：US20120168947A1
公开(公告)日：2012-07-05
申请号：US13404317
申请日：2012-02-24
申请人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent C. Mancelita
发明人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent C. Mancelita
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L21/74 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05 , H01L2224/16 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
摘要翻译：描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。双向图案设计保持通道不与晶片的晶体取向对齐。然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。还描述了其它实施例。

9. 发明申请

US20110198689A1 SEMICONDUCTOR DEVICES CONTAINING TRENCH MOSFETS WITH SUPERJUNCTIONS 审中-公开
标题翻译：具有超级功能的具有TRENCH MOSFET的半导体器件
公开(公告)号：US20110198689A1
公开(公告)日：2011-08-18
申请号：US12707323
申请日：2010-02-17
申请人： Suku Kim
发明人： Suku Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734
摘要： Semiconductor devices combining a MOSFET architecture with a PN super-junction structure and methods for making such devices are described. The MOSFET architecture can be made using a trench configuration containing a gate that is sandwiched between thick dielectric layers in the top and the bottom of the trench. The PN junction of the super-junction structure is formed between n-type dopant regions in the sidewalls of the trench and a p-type epitaxial layer. The gate of the trench MOSFET is separated from the super-junction structure using a gate insulating layer. Such semiconductor devices can have a lower capacitance and a higher breakdown voltage relative to shield-based trench MOSFET devices and can replace such devices in medium to high voltage ranges. Other embodiments are described.
摘要翻译：描述了结合MOSFET结构与PN超结结构的半导体器件以及用于制造这种器件的方法。 MOSFET结构可以使用包含夹在沟槽的顶部和底部中的厚电介质层之间的栅极的沟槽配置来制造。超结结构的PN结形成在沟槽的侧壁中的n型掺杂区域和p型外延层之间。使用栅绝缘层将沟槽MOSFET的栅极与超结结构分离。相对于基于屏蔽的沟槽MOSFET器件，这样的半导体器件可以具有较低的电容和更高的击穿电压，并且可以在中等至高电压范围内替代这样的器件。描述其他实施例。

10. 发明申请

US20090273082A1 METHODS AND DESIGNS FOR LOCALIZED WAFER THINNING 有权
标题翻译：本地化方法和设计方法
公开(公告)号：US20090273082A1
公开(公告)日：2009-11-05
申请号：US12115254
申请日：2008-05-05
申请人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent Mancelita
发明人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent Mancelita
IPC分类号： H01L23/488 , H01L21/768
CPC分类号： H01L21/74 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05 , H01L2224/16 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
摘要翻译：描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。双向图案设计保持通道不与晶片的晶体取向对齐。然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。还描述了其它实施例。

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