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1. 发明授权

US08058732B2 Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same 失效
标题翻译：用于晶圆级芯片尺寸封装的半导体晶片结构，用于使用它们的功率器件，封装和系统及其制造方法
公开(公告)号：US08058732B2
公开(公告)日：2011-11-15
申请号：US12275086
申请日：2008-11-20
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
IPC分类号： H01L23/48
CPC分类号： H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

2. 发明申请

US20100123225A1 Semiconductor Die Structures for Wafer-Level Chipscale Packaging of Power Devices, Packages and Systems for Using the Same, and Methods of Making the Same 失效
标题翻译：用于晶圆级芯片尺寸的半导体晶片结构，功率器件，封装及其使用系统及其制作方法
公开(公告)号：US20100123225A1
公开(公告)日：2010-05-20
申请号：US12275086
申请日：2008-11-20
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

3. 发明授权

US08598035B2 Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same 有权
标题翻译：具有填充弹性材料的后侧沟槽的半导体裸片，用于改善附着，使用其的封装及其制造方法
公开(公告)号：US08598035B2
公开(公告)日：2013-12-03
申请号：US13151495
申请日：2011-06-02
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L21/44
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

4. 发明申请

US20110230046A1 SEMICONDUCTOR DICE WITH BACKSIDE TRENCHES FILLED WITH ELASTIC MATERIAL FOR IMPROVED ATTACHMENT, PACKAGES USING THE SAME, AND METHODS OF MAKING THE SAME 有权
标题翻译：具有用于改进附件的用弹性材料填充的背面斜面的半导体切片，使用其的包装及其制造方法
公开(公告)号：US20110230046A1
公开(公告)日：2011-09-22
申请号：US13151495
申请日：2011-06-02
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L21/28
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

5. 发明授权

US07960800B2 Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same 有权
标题翻译：具有填充弹性材料的后侧沟槽的半导体裸片，用于改善附着，使用其的封装及其制造方法
公开(公告)号：US07960800B2
公开(公告)日：2011-06-14
申请号：US12334331
申请日：2008-12-12
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L27/088
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

6. 发明申请

US20100148325A1 Semiconductor Dice with Backside Trenches Filled With Elastic Material For Improved Attachment, Packages Using the Same, and Methods of Making the Same 有权
标题翻译：具有填充弹性材料的背面槽的半导体骰子用于改善附件，使用其的包装及其制造方法
公开(公告)号：US20100148325A1
公开(公告)日：2010-06-17
申请号：US12334331
申请日：2008-12-12
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L23/495 , H01L23/498 , H01L21/768
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

7. 发明申请

US20100308402A1 3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的3D通道架构
公开(公告)号：US20100308402A1
公开(公告)日：2010-12-09
申请号：US12480065
申请日：2009-06-08
申请人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
发明人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

8. 发明授权

US08072027B2 3D channel architecture for semiconductor devices 有权
标题翻译：半导体器件的3D通道架构
公开(公告)号：US08072027B2
公开(公告)日：2011-12-06
申请号：US12480065
申请日：2009-06-08
申请人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
发明人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

9. 外观设计

USD312714S Combined waxer and polisher tool 失效
公开(公告)号：USD312714S
公开(公告)日：1990-12-04
申请号：US341067
申请日：1989-04-20
申请人： Robert Simonelli , Mark Larsen , Kiyoshi Iha
设计人： Robert Simonelli , Mark Larsen , Kiyoshi Iha

10. 发明申请

US20050063356A1 Power adaption in a multi-station network 失效
标题翻译：多站网络中的电源适配
公开(公告)号：US20050063356A1
公开(公告)日：2005-03-24
申请号：US10960244
申请日：2004-10-07
申请人： Mark Larsen , James Larsen
发明人： Mark Larsen , James Larsen
IPC分类号： H04B7/005 , H04B7/26 , H04L12/00 , H04L12/26 , H04L12/721 , H04L12/28
CPC分类号： H04W52/243 , H04L43/08 , H04L43/0829 , H04L43/0852 , H04L43/0864 , H04L43/10 , H04L43/12 , H04L45/70 , H04W16/14 , H04W24/00 , H04W52/0219 , H04W52/0245 , H04W52/04 , H04W52/10 , H04W52/223 , H04W52/226 , H04W52/228 , H04W52/242 , H04W52/246 , H04W52/247 , H04W52/46 , H04W72/08
摘要： The invention relates to a method of operating a communication network, the network comprising a plurality of stations which are able to transmit data to and receive data from one another. The method comprises monitoring, at each station, the transmission path quality between that station and each other station with which that station can communicate. Data corresponding to the monitored path quality is recorded at each station, thereby permitting a transmission power value based on the relevant path quality data to be selected when transmitting data to another station. Thus, the probability of transmitting data to any selected station at an optimum power level is increased. Each station transmits path quality data in its own transmissions as well as local noise/interference data, so that other stations can obtain path quality data for a particular station even if they are out of range of that particular station. The invention extends to communication apparatus which can be used to implement the method.
摘要翻译：本发明涉及一种操作通信网络的方法，该网络包括能够将数据彼此传输和接收数据的多个站。该方法包括在每个站处监测该站与该站可以与之通信的每个其他站之间的传输路径质量。在每个站处记录与被监视的路径质量对应的数据，从而当向另一站发送数据时，允许基于相关路径质量数据的发送功率值被选择。因此，以最佳功率电平将数据发送到任何选择的站的概率增加。每个站在其自己的传输中传送路径质量数据以及本地噪声/干扰数据，使得其他站可以获得特定站的路径质量数据，即使它们在该特定站的范围之外。本发明延伸到可用于实现该方法的通信设备。

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