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1. 发明授权

US06809852B2 Microsystem package structure 有权
标题翻译：微系统封装结构
公开(公告)号：US06809852B2
公开(公告)日：2004-10-26
申请号：US10603957
申请日：2003-06-24
申请人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
发明人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
IPC分类号： G02B2600
CPC分类号： G02B7/1821 , H01L2224/16145 , H01L2224/32225 , H01L2224/73265 , H01L2924/00014 , H01L2224/0401
摘要： The present invention relates to a package structure for a microsystem, comprising a substrate, a chip, an adhesive structure, a carrying substrate, a micro-mechanism, a plurality of wires, an annular body and a transparent plate. The chip is placed on the substrate. The annular adhesive structure having an opening is placed on the chip. The carrying substrate is placed on the adhesive structure, thus forming an interspace between the chip, the adhesive structure and the carrying substrate. The pressure inside the interspace can be balanced with the pressure outside the interspace through the opening. The micro-mechanism is disposed on the carrying substrate. The annular body is formed on the substrate and the transparent plate is attached on the annular body, thus forming a closed chamber between the substrate, the annular body and the transparent plate. The chip, the micro-mechanism, the adhesive structure, the carrying substrate and the wires are disposed within the closed chamber.
摘要翻译：本发明涉及一种用于微系统的封装结构，其包括基板，芯片，粘合结构，承载基板，微机构，多根导线，环形体和透明板。将芯片放置在基板上。具有开口的环形粘合剂结构被放置在芯片上。携带衬底被放置在粘合剂结构上，从而在芯片，粘合剂结构和承载衬底之间形成间隙。间隙内的压力可以通过开口与间隙外的压力平衡。微机构设置在承载基板上。环状体形成在基板上，透明板安装在环状体上，由此在基板，环状体和透明板之间形成封闭室。芯片，微机构，粘合剂结构，承载基板和电线设置在封闭室内。

2. 发明授权

US06822324B2 Wafer-level package with a cavity and fabricating method thereof 有权
标题翻译：具有腔体的晶片级封装及其制造方法
公开(公告)号：US06822324B2
公开(公告)日：2004-11-23
申请号：US10352042
申请日：2003-01-28
申请人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
发明人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
IPC分类号： H01L2310
CPC分类号： H01L23/055 , H01L23/04 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01079 , H01L2924/07811 , H01L2924/15311 , H01L2924/16235 , H01L2924/00 , H01L2224/05599
摘要： A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.
摘要翻译：具有空腔的晶片级封装包括芯片，基板和密封构件。芯片具有微型器件和电连接到微器件的多个接合焊盘。衬底具有对应并电连接到接合焊盘的多个通孔导电孔。芯片上的每个接合焊盘设置有用于将焊盘电连接到导电通孔的导电凸块。密封构件围绕包装以形成密封腔。本发明还提供一种用于制造具有空腔的晶片级封装的方法。

3. 发明授权

US07002257B2 Optical component package and packaging including an optical component horizontally attached to a substrate 有权
标题翻译：光学部件封装和包装，其包括水平地附接到基板的光学部件
公开(公告)号：US07002257B2
公开(公告)日：2006-02-21
申请号：US10463578
申请日：2003-06-18
申请人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao
发明人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao
IPC分类号： H01L23/28
CPC分类号： H01L27/14618 , H01L24/29 , H01L24/32 , H01L24/73 , H01L27/14683 , H01L31/0203 , H01L31/0232 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/15787 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.
摘要翻译：光学部件封装包括基板，光学部件，多个间隔件，多根电线以及透明模塑料。光学部件设置在基板上，并且使用远离基板的光学部件的表面来接收光信号。间隔件设置在基板和光学部件之间。电线将光学部件电连接到基板。透明模塑料封装光学部件。在这种情况下，每个间隔物的直径等于透明模塑料的厚度减去光学部件的厚度减去光信号进入透明模塑料之间的距离，并且光信号由光学元件。此外，本发明还公开了一种用于光学部件封装的封装方法。

4. 发明授权

US07247267B2 Mold and method of molding semiconductor devices 有权
标题翻译：模具和模制半导体器件的方法
公开(公告)号：US07247267B2
公开(公告)日：2007-07-24
申请号：US10710906
申请日：2004-08-12
申请人： Jen-Chieh Kao , Kuo-Chung Yee
发明人： Jen-Chieh Kao , Kuo-Chung Yee
IPC分类号： B29C70/72 , H01L21/56
CPC分类号： B29C45/0025 , B29C45/14639 , H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.
摘要翻译：提供了一种用于模制安装在封装衬底上的半导体器件的模具。模具包括顶模和底模。顶部模具具有顶部流道，至少第一模拟流道和多个模具腔。第一个虚拟跑步者与顶级跑步者相连，顶级赛跑者延伸到模具腔之间的空间。用于容纳半导体器件的模腔连接到顶部流道。底模具有底流道和至少第二模拟流道。第二个虚拟跑步者与底下的跑步者相连。第二虚拟跑步者位于上方，但是通过封装衬底与第一虚拟跑步者分离。

5. 发明申请

US20070004087A1 CHIP PACKAGING PROCESS 审中-公开
标题翻译：芯片包装工艺
公开(公告)号：US20070004087A1
公开(公告)日：2007-01-04
申请号：US11306049
申请日：2005-12-15
申请人： Jen-Chieh Kao , Kuo-Chung Yee
发明人： Jen-Chieh Kao , Kuo-Chung Yee
IPC分类号： H01L21/00
CPC分类号： H01L31/0203 , H01L24/94 , H01L27/14687 , H01L31/1876 , Y02E10/50 , Y02P70/521
摘要： A chip packaging process is provided. First, a matrix package substrate having a carrying surface with a plurality of scribe lines thereon is provided. The scribe lines divide the package substrate into a plurality of package substrate units. Then, a sealant is formed on each scribe line. A chip is disposed on each package substrate unit. Furthermore, the chip is electrically connected to a corresponding package substrate unit. Thereafter, a transparent cover is disposed over the matrix package substrate. The transparent cover and the matrix package substrate are connected via the sealant. After that, a trimming process along the scribe lines is performed to cut the transparent cover, the matrix package substrate and the sealant.
摘要翻译：提供了芯片封装工艺。首先，提供具有其上具有多个划线的承载面的矩阵封装基板。划线将封装衬底分成多个封装衬底单元。然后，在每个划线上形成密封剂。芯片设置在每个封装基板单元上。此外，芯片电连接到相应的封装衬底单元。此后，在矩阵封装基板上设置透明盖。透明盖和矩阵封装基板通过密封剂连接。之后，进行沿着划线的修整处理，以切割透明盖，矩阵封装基板和密封剂。

6. 发明申请

US20050037104A1 [MOLD AND METHOD OF MOLDING SEMICONDUCTOR DEVICES] 有权
标题翻译： [模具和半导体器件的成型方法]
公开(公告)号：US20050037104A1
公开(公告)日：2005-02-17
申请号：US10710906
申请日：2004-08-12
申请人： Jen-Chieh Kao , Kuo-Chung Yee
发明人： Jen-Chieh Kao , Kuo-Chung Yee
IPC分类号： B29C45/00 , B29C45/14 , H01L21/56
CPC分类号： B29C45/0025 , B29C45/14639 , H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.
摘要翻译：提供了一种用于模制安装在封装衬底上的半导体器件的模具。模具包括顶模和底模。顶部模具具有顶部流道，至少第一模拟流道和多个模具腔。第一个虚拟跑步者与顶级跑步者相连，顶级赛跑者延伸到模具腔之间的空间。用于容纳半导体器件的模腔连接到顶部流道。底模具有底流道和至少第二模拟流道。第二个虚拟跑步者与底下的跑步者相连。第二虚拟跑步者位于上方，但是通过封装衬底与第一虚拟跑步者分离。

7. 发明申请

US20100200974A1 SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME 审中-公开
标题翻译：使用相同的半导体封装结构
公开(公告)号：US20100200974A1
公开(公告)日：2010-08-12
申请号：US12505071
申请日：2009-07-17
申请人： Chao-Fu Weng , Tsung-Yueh Tsai , Chang-Ying Hung , Jen-Chieh Kao
发明人： Chao-Fu Weng , Tsung-Yueh Tsai , Chang-Ying Hung , Jen-Chieh Kao
IPC分类号： H01L23/52 , H01L23/49 , H01L23/28
CPC分类号： H01L24/05 , H01L23/3121 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/0516 , H01L2224/05164 , H01L2224/05166 , H01L2224/05181 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/73265 , H01L2225/06506 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2924/00012
摘要： A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.
摘要翻译：提供了使用其的半导体封装结构。半导体封装结构包括第一半导体元件，第二半导体元件，绑定线和模制化合物。第一半导体元件包括半导体管芯和焊盘。焊盘设置在半导体管芯的上方，并且包括金属基底，设置在金属基底上方的硬金属层和设置在硬金属层上方的抗氧化金属层。硬质金属层的硬度大于金属基体的硬度。抗氧化金属层的活性低于硬质金属层的活性。第一半导体元件设置在第二半导体元件上方。接合线连接到焊盘和第二半导体元件。成型复合体密封第一半导体元件和接合线并覆盖第二半导体元件。

8. 发明申请

US20090075027A1 MANUFACTURING PROCESS AND STRUCTURE OF A THERMALLY ENHANCED PACKAGE 有权
标题翻译：一种热增强包装的制造工艺和结构
公开(公告)号：US20090075027A1
公开(公告)日：2009-03-19
申请号：US12183398
申请日：2008-07-31
申请人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
发明人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
IPC分类号： B32B3/24 , B32B37/00 , B32B38/04 , B32B15/04 , B32B3/00
CPC分类号： B32B37/226 , B32B38/0004 , B32B2305/076 , B32B2305/342 , B32B2311/00 , B32B2315/085 , B32B2457/00 , H01L21/561 , H01L23/295 , H01L23/3128 , H01L23/4334 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , Y10T156/10 , Y10T156/1052 , Y10T428/24331 , Y10T428/24612 , Y10T428/31678 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.
摘要翻译：公开了一种用于热增强包装的制造方法。首先，提供至少包括基板的基板条。接下来，在基板的上表面上设置至少一个芯片，并且芯片与基板电连接。然后，设置预浸料和散热金属层，散热金属层设置在预浸料坯的第一表面上，并且预浸料坯的第二表面面向芯片。最后，预浸料通过层压预浸料和基材覆盖芯片。

9. 发明授权

US08059422B2 Thermally enhanced package structure 有权
标题翻译：热增强包装结构
公开(公告)号：US08059422B2
公开(公告)日：2011-11-15
申请号：US12183398
申请日：2008-07-31
申请人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
发明人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
IPC分类号： H05K1/18
CPC分类号： B32B37/226 , B32B38/0004 , B32B2305/076 , B32B2305/342 , B32B2311/00 , B32B2315/085 , B32B2457/00 , H01L21/561 , H01L23/295 , H01L23/3128 , H01L23/4334 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , Y10T156/10 , Y10T156/1052 , Y10T428/24331 , Y10T428/24612 , Y10T428/31678 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.
摘要翻译：公开了一种用于热增强包装的制造方法。首先，提供至少包括基板的基板条。接下来，在基板的上表面上设置至少一个芯片，并且芯片与基板电连接。然后，设置预浸料和散热金属层，散热金属层设置在预浸料坯的第一表面上，并且预浸料坯的第二表面面向芯片。最后，预浸料通过层压预浸料和基材覆盖芯片。

10. 发明授权

US07614888B2 Flip chip package process 有权
标题翻译：倒装芯片封装过程
公开(公告)号：US07614888B2
公开(公告)日：2009-11-10
申请号：US12237052
申请日：2008-09-24
申请人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
发明人： Ho-Ming Tong , Shin-Hua Chao , Ming-Chiang Lee , Tai-Yuan Huang , Chao-Yuan Liu , Yung-Cheng Huang , Teck-Chong Lee , Jen-Chieh Kao , Jau-Shoung Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/561 , H01L21/4853 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L24/81 , H01L24/97 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2224/97 , H01L2924/01023 , H01L2924/01033 , H01L2924/15311 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.
摘要翻译：提供了一种倒装芯片封装工艺。首先，提供包括至少一个基板的基板条。接下来，在基板上设置至少一个芯片，并且芯片与基板电连接。然后，具有至少一个开口和空气狭缝孔的模板设置在基板条的上表面上，在模板和基板条之间形成气隙，气隙连接开口和空气槽孔，芯片位于开口处。最后，将液体化合物形成在模板的开口中以封装芯片，并且通过空气槽孔和气隙进行真空处理，以防止开口内的空气被液体化合物包封变成空洞。

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