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1. 发明授权

US07151317B2 Multi-chip package structure 有权
标题翻译：多芯片封装结构
公开(公告)号：US07151317B2
公开(公告)日：2006-12-19
申请号：US10904404
申请日：2004-11-09
申请人： Shin-Hua Chao , Jian-Wen Lo
发明人： Shin-Hua Chao , Jian-Wen Lo
IPC分类号： H01L23/48
CPC分类号： H01L25/0652 , H01L24/14 , H01L24/17 , H01L2224/05571 , H01L2224/05573 , H01L2224/14131 , H01L2224/14135 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17505 , H01L2224/81986 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2924/00013 , H01L2924/00014 , H01L2924/014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.
摘要翻译：提供了包括第一芯片，图案化层压层，多个第一凸块，第二芯片和第二凸块的多芯片封装结构。第一芯片具有第一活性表面。图案化层压层设置在第一活性表面的一部分区域上。第一芯片具有多个第一接合焊盘，其设置在由图案化层压层暴露的第一有源表面上，并且图案化层叠层具有设置在其上的多个第二接合焊盘。第二芯片具有第二有源表面，并且第一突起设置在第二有源表面上。第二芯片通过第一凸块电连接到第一焊盘。第二凸块设置在第二接合焊盘上。此外，多芯片封装结构还包括设置在第一芯片上并与第一焊盘电连接的部件。

2. 发明申请

US20060103020A1 REDISTRIBUTION LAYER AND CIRCUIT STRUCTURE THEREOF 审中-公开
标题翻译：重新分配层和电路结构
公开(公告)号：US20060103020A1
公开(公告)日：2006-05-18
申请号：US11163815
申请日：2005-10-31
申请人： Ho-Ming Tong , Shin-Hua Chao , Chi-Yu Wang , Cherry Mercado Reyes
发明人： Ho-Ming Tong , Shin-Hua Chao , Chi-Yu Wang , Cherry Mercado Reyes
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , H01L23/3114 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05569 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/13 , H01L2224/13099 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00 , H01L2924/00014
摘要： A circuit structure of a redistribution layer (RDL) is suitable for a chip to define the circuits and the contact window required by the following bump process. The RDL is disposed on the active surface of the chip. The circuit structure of the RDL mainly includes a first titanium layer, a second titanium layer and a conductive layer. Wherein, the conductive layer is made of aluminum; the first titanium layer and the second titanium layer cover the two surfaces of the conductive layer, respectively. The connectivity between the first titanium layer or the second titanium layer and a macromolecule polymer is stronger than the connectivity between the conductive layer and the macromolecule polymer, so that the peeling or crack caused by poor connectivity between the conductive layer and the adjacent dielectric layers are significantly improved thereby.
摘要翻译：再分配层（RDL）的电路结构适用于芯片来定义随后的凸块工艺所需的电路和接触窗口。 RDL设置在芯片的有源表面上。 RDL的电路结构主要包括第一钛层，第二钛层和导电层。其中，导电层由铝制成; 第一钛层和第二钛层分别覆盖导电层的两个表面。第一钛层或第二钛层与高分子聚合物之间的连接性比导电层和高分子聚合物之间的连通性更强，导致导电层和相邻电介质层之间连接性差的剥离或裂纹是从而显着改善。

3. 发明授权

US07041534B2 Semiconductor chip package and method for making the same 有权
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US07041534B2
公开(公告)日：2006-05-09
申请号：US10926334
申请日：2004-08-26
申请人： Shin Hua Chao , Jen Kuang Fang , Ho Ming Tong
发明人： Shin Hua Chao , Jen Kuang Fang , Ho Ming Tong
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L24/19 , H01L23/5389 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2224/82 , H01L2924/00
摘要： A semiconductor chip package mainly includes a semiconductor chip, a first dielectric layer disposed on the semiconductor chip, a plurality of conductive traces electrically connected to the semiconductor chip, a second dielectric layer disposed on the conductive traces and the first dielectric layer wherein a portion of the conductive traces are exposed from the second dielectric layer, and a plurality of contacts for external connection formed on the exposed portion of the conductive traces. The semiconductor chip has a surface including an active area, a dummy area surrounding the active area, and a plurality of bonding pads disposed on the active area. The bonding pads are electrically connected to the contacts by the conductive traces. The present invention further provides methods for manufacturing the semiconductor chip package.
摘要翻译：半导体芯片封装主要包括半导体芯片，设置在半导体芯片上的第一介电层，与半导体芯片电连接的多个导电迹线，设置在导电迹线上的第二介电层和第一介电层，其中一部分导电迹线从第二介质层露出，并且在导电迹线的暴露部分上形成多个用于外部连接的触点。半导体芯片具有包括有源区域，围绕有源区域的虚拟区域以及设置在有源区域上的多个接合焊盘的表面。接合焊盘通过导电迹线电连接到触点。本发明还提供了制造半导体芯片封装的方法。

4. 发明授权

US06918178B2 Method of attaching a heat sink to an IC package 有权
标题翻译：将散热器连接到IC封装的方法
公开(公告)号：US06918178B2
公开(公告)日：2005-07-19
申请号：US10345929
申请日：2003-01-17
申请人： Shin-Hua Chao , Shyh-Ing Wu , Kuan-Neng Liao , Gin-Nan Yeh
发明人： Shin-Hua Chao , Shyh-Ing Wu , Kuan-Neng Liao , Gin-Nan Yeh
IPC分类号： H01L21/56 , H01L23/34 , H01L23/433 , H05K3/30
CPC分类号： H01L21/565 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , Y10T29/4913 , Y10T29/49139 , Y10T29/49146 , Y10T29/49158 , Y10T29/49798 , Y10T83/0457 , Y10T83/0538 , Y10T83/2079 , H01L2224/85 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.
摘要翻译：一种将散热器整体地连接到IC封装上以提高封装的导热性的改进方法。可分离成多个单独的散热器的散热器矩阵被附接到IC封装矩阵，IC封装矩阵由多个单独的IC封装组成，以矩阵方式彼此邻接。然后，通过机床将IC封装矩阵和附接到其上的散热器矩阵同时切割成多个单独形成的IC封装，每个IC封装均附着有散热片; 从而提高了传统IC封装的导热性。

5. 发明申请

US20050019965A1 Process for testing IC wafer 审中-公开
标题翻译： IC晶圆测试工艺
公开(公告)号：US20050019965A1
公开(公告)日：2005-01-27
申请号：US10895061
申请日：2004-07-21
申请人： Shin-Hua Chao , Yao-Hsin Feng
发明人： Shin-Hua Chao , Yao-Hsin Feng
IPC分类号： G01R31/28 , H01L21/301 , H01L23/58
CPC分类号： H01L22/32 , G01R31/2831 , G01R31/2856
摘要： A process for testing IC wafer is disclosed. Prior to electrically testing chips on a wafer, the wafer is pre-cut to form a plurality of grooves aligned with the scribe lines on the active surface of the wafer. A step of singulating the wafer is performed to form a plurality of individual chips after completing electrical or reliability test of the chips. Due to the pre-cutting step the chips are still integrated on the wafer for accurately probing and testing. And the testing step can obtain the influence of side chipping on the chips
摘要翻译：公开了一种用于测试IC晶片的方法。在晶片上的芯片电气测试之前，预先切割晶片以形成与晶片的有效表面上的划线对准的多个凹槽。在完成芯片的电气或可靠性测试之后，进行单晶化步骤以形成多个独立的芯片。由于预切割步骤，芯片仍然集成在晶圆上以进行准确的探测和测试。并且测试步骤可以获得芯片边缘切片的影响

6. 发明授权

US06348729B1 Semiconductor chip package and manufacturing method thereof 有权
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US06348729B1
公开(公告)日：2002-02-19
申请号：US09390695
申请日：1999-09-07
申请人： Sai Man Li , Chun Hung Lin , Shin Hua Chao , Su Tao
发明人： Sai Man Li , Chun Hung Lin , Shin Hua Chao , Su Tao
IPC分类号： H01L2352
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01077 , H01L2924/01079 , H01L2924/181 , H01L2924/18165 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.
摘要翻译：半导体芯片封装通常包括引线框架，半导体管芯和塑料封装体。引线框架包括多个引线和窗垫。窗垫通过连接杆连接到引线框架。多个引线的内端限定中心区域。窗垫设置在中心区域中并且具有限定在其中的开口。半导体管芯设置在窗垫的开口中，并且在其活性表面上形成有多个接合焊盘。引线的内端通过多根接合线与半导体管芯上的焊盘相互连接。引线框架，半导体管芯和接合线被封装在塑料封装主体中，其中引线框架的下表面和半导体管芯的后表面通过塑料封装主体露出。

7. 发明申请

US20120032341A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20120032341A1
公开(公告)日：2012-02-09
申请号：US12947390
申请日：2010-11-16
申请人： Shin-Hua CHAO , Chao-Yuan LIU , Hui-Ying HSIEH , Chih-Ming CHUNG
发明人： Shin-Hua CHAO , Chao-Yuan LIU , Hui-Ying HSIEH , Chih-Ming CHUNG
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/96 , H01L21/56 , H01L23/145 , H01L23/295 , H01L23/3128 , H01L23/49811 , H01L24/16 , H01L24/97 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/3511 , H01L2224/81 , H01L2924/00
摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.
摘要翻译：提供半导体封装及其制造方法。半导体封装包括衬底，半导体元件，封装体和导电部件。基板具有电接触。半导体元件设置在基板上。封装体覆盖半导体元件并且限定了电触头暴露的通孔。其中，包装体包括树脂体和多个纤维层。纤维层设置在树脂体中并限定多个布置成阵列的纤维孔。导电部件通过通孔与基板电连接。

8. 发明申请

US20100289133A1 Stackable Package Having Embedded Interposer and Method for Making the Same 审中-公开
标题翻译：具有嵌入式内插器的可堆叠封装及其制作方法
公开(公告)号：US20100289133A1
公开(公告)日：2010-11-18
申请号：US12727770
申请日：2010-03-19
申请人： Shin-Hua Chao , Teck-Chong Lee , Shing-Cheng Liang
发明人： Shin-Hua Chao , Teck-Chong Lee , Shing-Cheng Liang
IPC分类号： H01L23/488 , H01L21/60 , H01L23/498
CPC分类号： H01L23/5389 , H01L21/56 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/48 , H01L25/105 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a stackable package having an embedded interposer and a method for making the same. The package includes a substrate, a chip, a first embedded interposer, a circuit layer and a solder mask. The substrate has an upper surface, a bottom surface and at least one connecting pad. The connecting pad is disposed adjacent to the upper surface. The chip is disposed adjacent to the upper surface of the substrate, and is electrically connected to the substrate. The first embedded interposer encapsulates the upper surface of the substrate and the chip. The to first embedded interposer includes at least one plating through hole. The plating through hole penetrates through the first embedded interposer, and is connected to the connecting pad of the substrate. The circuit layer is disposed adjacent to the first embedded interposer, and the plating through hole is connected to the circuit layer. The circuit layer includes at least one pad. The solder mask is disposed adjacent to the circuit layer, and exposes the pad. Therefore, the package has more pads for inputting/outputting, more flexibility for stacking a top package, and a reduced total thickness.
摘要翻译：本发明涉及具有嵌入式插入器的可堆叠封装及其制造方法。封装包括衬底，芯片，第一嵌入式插入器，电路层和焊接掩模。基板具有上表面，底表面和至少一个连接垫。连接垫邻近上表面设置。芯片靠近基板的上表面设置，并与基板电连接。第一嵌入式插入器封装衬底和芯片的上表面。第一嵌入式插入器包括至少一个电镀通孔。电镀通孔穿过第一嵌入式插入器，并连接到衬底的连接焊盘。电路层与第一嵌入式插入件相邻设置，电镀通孔与电路层连接。电路层包括至少一个焊盘。焊接掩模邻近电路层设置，并露出焊盘。因此，封装具有更多的用于输入/输出的焊盘，用于堆叠顶部封装的更大的灵活性和更小的总厚度。

9. 发明申请

US20050199991A1 MULTI-CHIP PACKAGE STRUCTURE 有权
标题翻译：多芯片包装结构
公开(公告)号：US20050199991A1
公开(公告)日：2005-09-15
申请号：US10904404
申请日：2004-11-09
申请人： Shin-Hua Chao , Jian-Wen Lo
发明人： Shin-Hua Chao , Jian-Wen Lo
IPC分类号： H01L23/48
CPC分类号： H01L25/0652 , H01L24/14 , H01L24/17 , H01L2224/05571 , H01L2224/05573 , H01L2224/14131 , H01L2224/14135 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17505 , H01L2224/81986 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2924/00013 , H01L2924/00014 , H01L2924/014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.
摘要翻译：提供了包括第一芯片，图案化层压层，多个第一凸块，第二芯片和第二凸块的多芯片封装结构。第一芯片具有第一活性表面。图案化层压层设置在第一活性表面的一部分区域上。第一芯片具有多个第一接合焊盘，其设置在由图案化层压层暴露的第一有源表面上，并且图案化层叠层具有设置在其上的多个第二接合焊盘。第二芯片具有第二有源表面，并且第一突起设置在第二有源表面上。第二芯片通过第一凸块电连接到第一焊盘。第二凸块设置在第二接合焊盘上。此外，多芯片封装结构还包括设置在第一芯片上并与第一焊盘电连接的部件。

10. 发明授权

US06355499B1 Method of making ball grid array package 有权
标题翻译：制造球栅阵列封装的方法
公开(公告)号：US06355499B1
公开(公告)日：2002-03-12
申请号：US09610859
申请日：2000-07-06
申请人： Shyh-Ing Wu , Shin Hua Chao , Yao Shin Fang
发明人： Shyh-Ing Wu , Shin Hua Chao , Yao Shin Fang
IPC分类号： H01L2144
CPC分类号： H01L23/3128 , H01L21/565 , H01L24/97 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method of making a ball grid array package comprises the steps of: (a) providing a film having an opening defined therein; (b) placing the film on a substrate; (c) attaching a semiconductor chip onto the substrate such that the semiconductor chip is positioned in the opening of the film; (d) electrically coupling the semiconductor chip to the substrate; (e) providing a molding die having a runner, a gate and a molding cavity defined therein, wherein the runner is connected to the molding cavity through the gate; (f) closing and clamping the molding die in a manner that the semiconductor chip is positioned in the molding cavity wherein the edges of the molding cavity fit entirely within the opening of the film and the edges of the runners and the gates are entirely positioned against the film; (g) transferring a hardenable molding compound into the molding cavity; (h) hardening the molding compound; (i) unclamping and opening the molding die; and (j) simultaneously removing the film and degating. The film in accordance with the present invention is characterized in that the adhesive force between the film and the molding compound is greater than the adhesive force between the film and the substrate. This makes the film tend to adhere to the excess molding compound; hence, the film will be removed along with the excess molding compound during the step (j) thereby automating the molding process.
摘要翻译：制造球栅阵列封装的方法包括以下步骤：（a）提供其中限定有开口的膜; （b）将膜放置在基底上; （c）将半导体芯片附着在基板上，使得半导体芯片位于膜的开口中; （d）将半导体芯片电耦合到基板; （e）提供具有限定在其中的流道，浇口和模制腔的模具，其中流道通过浇口连接到模腔; （f）以半导体芯片定位在模制腔中的方式闭合和夹紧模具，其中模制空腔的边缘完全配合在薄膜的开口内，并且流道和浇口的边缘完全被定位成抵抗这个电影; （g）将可硬化的模塑料转移到模腔中; （h）硬化模塑料; （i）松开和打开成型模具; 和（j）同时除去膜并脱胶。根据本发明的膜的特征在于，膜和模塑料之间的粘合力大于膜和基材之间的粘合力。这使得膜倾向于粘附到多余的模塑料上; 因此，在步骤（j）期间，膜将与多余的模塑料一起被去除，从而使模制过程自动化。

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