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1. 发明授权

US07283556B2 Method and system for managing time division multiplexing (TDM) timeslots in a network switch 失效
标题翻译：用于管理网络交换机中的时分复用（TDM）时隙的方法和系统
公开(公告)号：US07283556B2
公开(公告)日：2007-10-16
申请号：US10209158
申请日：2002-07-31
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/43
CPC分类号： H04L49/103 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/357 , H04Q11/04 , H04Q2213/13292 , H04Q2213/13296 , H04Q2213/13332 , H04Q2213/13389
摘要： A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e.g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.
摘要翻译：一种用于管理网络交换机中时分多路复用（TDM）时隙分配的系统和方法。网络交换机可以使用包括多个时隙的TDM周期来管理共享资源，并且通过当前配置的端口来调度数据入口和出口，其中每个端口被分配一个或多个时隙。网络交换机可以被重新编程以支持多个端口配置之一的多个时隙分配方案之一。网络交换机可以支持具有不同数量端口的配置，例如， 8和16端口配置。网络交换机还可以支持将两个或多个端口组合以形成一个端口（例如，2Gbs光纤通道端口）的配置。为了满足各种配置的要求，时隙分配方案可以被重新编程以满足每个可能的端口配置的调度要求。

2. 发明授权

US07809852B2 High jitter scheduling of interleaved frames in an arbitrated loop 失效
标题翻译：仲裁循环中交错帧的高抖动调度
公开(公告)号：US07809852B2
公开(公告)日：2010-10-05
申请号：US10152763
申请日：2002-05-22
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： G06F13/00
CPC分类号： H04L47/6215 , H04L12/433 , H04L47/22 , H04L47/283 , H04L47/50 , H04L47/6225 , H04L49/357
摘要： A system and method for converting low-jitter, interleaved frame traffic, such as that generated in an IP network, to high jitter traffic to improve the utilization of bandwidth on arbitrated loops such as Fibre Channel Arbitrated Loops. Embodiments of a high jitter scheduling algorithm may be used in devices such as network switches that interface an arbitrated loop with an IP network that carries low-jitter traffic. The high jitter algorithm may use a separate queue for each device on the arbitrated loop, or alternatively may use one queue for two or more devices. Incoming frames are distributed among the queues based upon each frame's destination device. The scheduling algorithm may then service the queues and forward queued frames to the devices from the queues. In one embodiment, the queues are serviced in a round-robin fashion. In one embodiment, each queue may be serviced for a programmed limit.
摘要翻译：将诸如IP网络中生成的低抖动交织帧流量转换为高抖动流量以提高诸如光纤通道仲裁环路之类的仲裁环路上的带宽利用率的系统和方法。高抖动调度算法的实施例可以用于诸如将仲裁环路与承载低抖动流量的IP网络相连接的网络交换机的设备。高抖动算法可以对仲裁环路上的每个设备使用单独的队列，或者可以为两个或更多个设备使用一个队列。基于每个帧的目的地设备，进入的帧被分配在队列之间。然后，调度算法可以对队列进行服务并将排队的帧从队列转发到设备。在一个实施例中，队列以循环方式服务。在一个实施例中，每个队列可以被服务于编程限制。

3. 发明授权

US07227841B2 Packet input thresholding for resource distribution in a network switch 失效
标题翻译：网络交换机资源分配的分组输入阈值
公开(公告)号：US07227841B2
公开(公告)日：2007-06-05
申请号：US10144081
申请日：2002-05-13
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： G01R31/08
CPC分类号： H04L47/32 , H04L47/29 , H04L47/50 , H04L49/103 , H04L49/108 , H04L49/30 , H04L49/90 , H04L49/901 , H04L49/9036 , H04L49/9094 , H04L2012/5681
摘要： A system and method for input thresholding packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the network switch may be assigned to one of a plurality of threshold groups and to one of a plurality of flows within the threshold group. In one embodiment, each threshold group may be divided into a plurality of levels of operation. As resources are allocated or freed by the threshold group, the threshold group may dynamically move up or down in the levels of operation. Within each level, one or more different values may be used as level boundaries and resource limits for flows within the threshold group. In one embodiment, programmable registers may be used to store these values.
摘要翻译：一种用于在网络交换机中输入阈值分组的系统和方法。网络交换机可以包括多个输入端口，多个输出端口以及通过数据传输逻辑耦合到输入端口和输出端口的共享随机存取存储器。可以将进入网络交换机的分组分配给多个阈值组中的一个和阈值组内的多个流中的一个。在一个实施例中，每个阈值组可被划分成多个操作级别。当资源由阈值组分配或释放时，阈值组可以在操作级别上动态上移或下移。在每个级别内，可以使用一个或多个不同的值作为阈值组内的流的级别边界和资源限制。在一个实施例中，可以使用可编程寄存器来存储这些值。

4. 发明授权

US07215680B2 Method and apparatus for scheduling packet flow on a fibre channel arbitrated loop 失效
标题翻译：用于在光纤信道仲裁环路上调度分组流的方法和装置
公开(公告)号：US07215680B2
公开(公告)日：2007-05-08
申请号：US10144187
申请日：2002-05-13
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/56
CPC分类号： H04L47/2433 , H04L47/50 , H04L47/56 , H04L47/6225 , H04L49/205 , H04L49/254 , H04L49/3018 , H04L49/351 , H04L49/357 , H04L67/1097 , H04L69/329
摘要： A system and method for enabling a network switch to transmit queued packets to a device when opened by the device, and thus to utilize the Fibre Channel Arbitrated Loop (FC-AL) in full-duplex mode when possible. The switch may include a plurality of queues each associated with a device on the FC-AL for queuing incoming packets for the device. The switch may determine a next non-empty queue, open the device associated with the queue, and send packets to the device. The device may send packets to the switch concurrently with receiving packets from the switch, thus utilizing the FC-AL in full-duplex mode. When a device opens the switch to transmit packets to the switch, the switch may determine if there are packets for the device in the queue and, if so, send packets to the device concurrently with receiving packets from the device, thus utilizing the FC-AL in full-duplex mode.
摘要翻译：一种用于使网络交换机能够在设备打开时将排队的分组传送到设备的系统和方法，并且因此在可能的情况下以全双工模式利用光纤通道仲裁环路（FC-AL）。交换机可以包括多个队列，每个队列与FC-AL上的设备相关联，用于对用于设备的输入分组进行排队。交换机可以确定下一个非空队列，打开与队列关联的设备，并将数据包发送到设备。设备可以同时从交换机接收数据包发送数据包，从而在全双工模式下利用FC-AL。当设备打开交换机向交换机发送数据包时，交换机可以确定队列中是否存在设备的数据包，如果是，则从设备接收数据包并发发送数据包，从而利用FC- AL在全双工模式。

5. 发明授权

US07406041B2 System and method for late-dropping packets in a network switch 失效
标题翻译：在网络交换机中丢包的系统和方法
公开(公告)号：US07406041B2
公开(公告)日：2008-07-29
申请号：US10209545
申请日：2002-07-31
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/26
CPC分类号： H04L47/30 , H04L47/10 , H04L47/2441 , H04L47/31 , H04L47/32 , H04L49/50
摘要： A system and method for late-dropping packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the switch may be subject to input thresholding, and may be assigned to a flow within a group. A portion of a packet subject to input thresholding may be accepted into the switch and assigned to a group and flow even if, at the time of arrival of the portion, there are not enough resources available to receive the remainder of the packet. This partial receipt of the packet is allowed because of the possibility of additional resources becoming available between the time of receipt of and resource allocation for the portion of the packet and receipt of subsequent portions of the packet.
摘要翻译：一种用于在网络交换机中后期丢包的系统和方法。网络交换机可以包括多个输入端口，多个输出端口以及通过数据传输逻辑耦合到输入端口和输出端口的共享随机存取存储器。进入交换机的数据包可能需要输入阈值，并且可以分配给组内的流。即使在部分到达时，没有足够的资源可用于接收分组的其余部分，经过输入阈值处理的分组的一部分也可被接收到交换机中并分配给组和流。允许分组的这种部分接收是因为在分组的接收时间和分组的部分和分组的后续部分的接收之间有额外的资源可用。

6. 发明申请

US20080080548A1 Method and System for Managing Time Division Multiplexing (TDM) Timeslots in a Network Switch 审中-公开
标题翻译：用于管理网络交换机中的时分复用（TDM）时隙的方法和系统
公开(公告)号：US20080080548A1
公开(公告)日：2008-04-03
申请号：US11871105
申请日：2007-10-11
申请人： Rodney Mullendore , Stuart Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney Mullendore , Stuart Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04B7/212
CPC分类号： H04L49/103 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/357 , H04Q11/04 , H04Q2213/13292 , H04Q2213/13296 , H04Q2213/13332 , H04Q2213/13389
摘要： A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e.g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.
摘要翻译：一种用于管理网络交换机中时分多路复用（TDM）时隙分配的系统和方法。网络交换机可以使用包括多个时隙的TDM周期来管理共享资源，并且通过当前配置的端口来调度数据入口和出口，其中每个端口被分配一个或多个时隙。网络交换机可以被重新编程以支持多个端口配置之一的多个时隙分配方案之一。网络交换机可以支持具有不同数量端口的配置，例如， 8和16端口配置。网络交换机还可以支持将两个或多个端口组合以形成一个端口（例如，2Gbs光纤通道端口）的配置。为了满足各种配置的要求，时隙分配方案可以被重新编程以满足每个可能的端口配置的调度要求。

7. 发明申请

US20080103753A1 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 审中-公开
公开(公告)号：US20080103753A1
公开(公告)日：2008-05-01
申请号：US11929450
申请日：2007-10-30
申请人： Suresh Rajan , Keith Schakel , Michael Sebastian Smith , David Wang , Frederick Weber
发明人： Suresh Rajan , Keith Schakel , Michael Sebastian Smith , David Wang , Frederick Weber
IPC分类号： G06F9/455
CPC分类号： G11C7/1072 , G06F13/4243 , G11C7/10 , G11C11/406 , G11C11/40618 , Y02D10/14 , Y02D10/151
摘要： A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

8. 发明申请

US20070192563A1 SYSTEM AND METHOD FOR TRANSLATING AN ADDRESS ASSOCIATED WITH A COMMAND COMMUNICATED BETWEEN A SYSTEM AND MEMORY CIRCUITS 有权
标题翻译：用于转换与系统和存储器电路之间通信的命令相关联的地址的系统和方法
公开(公告)号：US20070192563A1
公开(公告)日：2007-08-16
申请号：US11672924
申请日：2007-02-08
申请人： Suresh Rajan , Keith Schakel , Michael Smith , David Wang , Frederick Weber
发明人： Suresh Rajan , Keith Schakel , Michael Smith , David Wang , Frederick Weber
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F13/28 , G06F13/4243 , G11C11/406 , G11C11/40618 , G11C11/4093 , Y02D10/14 , Y02D10/151
摘要： A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.
摘要翻译：提供了一种存储器电路系统和方法。接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作地转换与在系统和存储器电路之间传送的命令相关联的地址。

9. 发明申请

US20080104314A1 MEMORY DEVICE WITH EMULATED CHARACTERISTICS 审中-公开
公开(公告)号：US20080104314A1
公开(公告)日：2008-05-01
申请号：US11929483
申请日：2007-10-30
申请人： Suresh Rajan , Keith Schakel , Michael Smith , David Wang , Frederick Weber
发明人： Suresh Rajan , Keith Schakel , Michael Smith , David Wang , Frederick Weber
IPC分类号： G06F12/02 , G06F9/455
CPC分类号： G11C7/1072 , G06F13/4243 , G11C7/10 , G11C11/406 , G11C11/40618 , Y02D10/14 , Y02D10/151
摘要： A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

10. 发明申请

US20080028136A1 METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES 审中-公开
公开(公告)号：US20080028136A1
公开(公告)日：2008-01-31
申请号：US11828181
申请日：2007-07-25
申请人： Keith Schakel , Suresh Rajan , Michael John Smith , David Wang
发明人： Keith Schakel , Suresh Rajan , Michael John Smith , David Wang
IPC分类号： G06F13/28
CPC分类号： G11C11/40615 , G06F13/1636 , G11C5/02 , G11C5/04 , G11C11/406 , G11C11/40611 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , Y02D10/14
摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

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