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1. 发明授权

US06628143B2 Full-swing source-follower leakage tolerant dynamic logic 有权
标题翻译：全摆动源跟踪器泄漏容错动态逻辑
公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
申请人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译：全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。

2. 发明授权

US07325024B2 Adder circuit with sense-amplifier multiplexer front-end 有权
标题翻译：加法器电路带有读出放大器多路复用器前端
公开(公告)号：US07325024B2
公开(公告)日：2008-01-29
申请号：US10728127
申请日：2003-12-04
申请人： Sanu K. Mathew , Mark A. Anders , Ram K. Krishnamurthy , Sapumal Wijeratne
发明人： Sanu K. Mathew , Mark A. Anders , Ram K. Krishnamurthy , Sapumal Wijeratne
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/506
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译：一个加法器电路包括多个选择器和一个加法器。选择器为加法器提供多个输入数据位。每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

3. 发明授权

US07840885B2 Distributed ring control circuits for Viterbi traceback 有权
标题翻译：用于维特比回溯的分布式环形控制电路
公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
申请人： Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译：移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。

4. 发明授权

US07352209B2 Voltage-level converter 有权
标题翻译：电压电平转换器
公开(公告)号：US07352209B2
公开(公告)日：2008-04-01
申请号：US11411647
申请日：2006-04-26
申请人： Steven K. Hsu , Mark A. Anders , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Mark A. Anders , Ram K. Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
摘要翻译：电压电平转换器包括静态电压电平转换器和耦合到静态电压电平转换器的分离电平输出电路。在另一实施例中，电压电平转换器包括静态电压电平转换器，第一晶体管和第二晶体管。静态电压电平转换器包括输入节点，第一上拉节点，第二上拉节点，逆变器输出节点和输出节点。第一晶体管耦合到输入节点和第一上拉节点。第二晶体管耦合到第二上拉节点和逆变器输出节点。

5. 发明授权

US07272029B2 Transition-encoder sense amplifier 有权
标题翻译：转换编码器读出放大器
公开(公告)号：US07272029B2
公开(公告)日：2007-09-18
申请号：US11025778
申请日：2004-12-29
申请人： Steven K. Hsu , Ram K. Krishnamurthy , Mark A. Anders
发明人： Steven K. Hsu , Ram K. Krishnamurthy , Mark A. Anders
IPC分类号： G11C11/00
CPC分类号： G11C7/08 , G11C7/065
摘要： A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
摘要翻译：读出放大器转换将输出信号编码到总线上，使得当感测到的位线具有与先前感测的位线的状态不同的状态时，总线信号仅转变。读出放大器包括当总线信号被断言时改变状态的存储元件。基于存储元件的状态，读出放大器的输出有条件地反转。

6. 发明授权

US07380099B2 Apparatus and method for an address generation circuit 有权
标题翻译：地址生成电路的装置和方法
公开(公告)号：US07380099B2
公开(公告)日：2008-05-27
申请号：US10956164
申请日：2004-09-30
申请人： Sanu K. Mathew , Mark A. Anders , Sarvesh H. Kulkarni , Ram Krishnamurthy
发明人： Sanu K. Mathew , Mark A. Anders , Sarvesh H. Kulkarni , Ram Krishnamurthy
IPC分类号： G06F12/00
CPC分类号： G06F7/507 , G06F7/508
摘要： A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.
摘要翻译：一种用于地址产生电路的方法和装置。在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。随后，从多个条件和中选出一个和，以在第二阶段中的第一阶段的逻辑地址分量和有效地址的第二部分中形成有效地址的第一部分。在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。描述和要求保护其他实施例。

7. 发明申请

US20150280909A1 Instruction and Logic for a Simon Block Cipher 有权
标题翻译：西门子密码的指令和逻辑
公开(公告)号：US20150280909A1
公开(公告)日：2015-10-01
申请号：US14227718
申请日：2014-03-27
申请人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
发明人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
IPC分类号： H04L9/08 , H04L9/14
CPC分类号： H04L9/0618 , G06F21/62 , G09C1/00 , H04L2209/24
摘要： A processor includes an input-circuit and a Simon block cipher. The Simon block cipher includes a data transformation circuit, a constant generator, and a key expansion circuit. The data transformation circuit includes logic to shift content of data storage registers. The key expansion circuit includes logic to determine a round key based upon an input symmetric key and data input, a previous round key, and a value from the constant generator. The constant generator includes logic to output a successive one of a list of constants each clock cycle, and to store the outputted constants in storage units. The number of storage units is less than the size of the list of constants.
摘要翻译：处理器包括输入电路和西门子分组密码。 Simon分组密码包括数据变换电路，恒定发生器和密钥扩展电路。数据变换电路包括移位数据存储寄存器的内容的逻辑。密钥扩展电路包括基于输入对称密钥和数据输入，先前的循环密钥和来自常量发生器的值来确定循环密钥的逻辑。常数发生器包括用于输出每个时钟周期的常数列表中的连续的一个的逻辑，并将输出的常数存储在存储单元中。存储单元的数量小于常量列表的大小。

8. 发明授权

US07509368B2 Sparse tree adder circuit 有权
标题翻译：稀疏树加法器电路
公开(公告)号：US07509368B2
公开(公告)日：2009-03-24
申请号：US11123702
申请日：2005-05-09
申请人： Mark A. Anders , Sanu K. Mathew , Nanda Siddaiah , Sapumal Wijeratne
发明人： Mark A. Anders , Sanu K. Mathew , Nanda Siddaiah , Sapumal Wijeratne
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/508
摘要： An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
摘要翻译：提供了一种加法器电路，其包括传播和产生电路级以提供传播和产生信号;多个进位合并级，用于基于传播和产生信号提供进位信号;以及条件和发生器，以基于传播和产生信号。条件和生成器包括纹波进位门和异或逻辑门。加法器电路还包括多个多路复用器，用于接收进位信号和条件和，并且基于输入信号提供输出。

9. 发明授权

US09473296B2 Instruction and logic for a simon block cipher 有权
标题翻译：一个simon块密码的指令和逻辑
公开(公告)号：US09473296B2
公开(公告)日：2016-10-18
申请号：US14227718
申请日：2014-03-27
申请人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
发明人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
IPC分类号： H04L9/06 , G06F21/62 , G09C1/00
CPC分类号： H04L9/0618 , G06F21/62 , G09C1/00 , H04L2209/24
摘要： A processor includes an input-circuit and a Simon block cipher. The Simon block cipher includes a data transformation circuit, a constant generator, and a key expansion circuit. The data transformation circuit includes logic to shift content of data storage registers. The key expansion circuit includes logic to determine a round key based upon an input symmetric key and data input, a previous round key, and a value from the constant generator. The constant generator includes logic to output a successive one of a list of constants each clock cycle, and to store the outputted constants in storage units. The number of storage units is less than the size of the list of constants.
摘要翻译：处理器包括输入电路和西门子分组密码。 Simon分组密码包括数据变换电路，恒定发生器和密钥扩展电路。数据变换电路包括移位数据存储寄存器的内容的逻辑。密钥扩展电路包括基于输入对称密钥和数据输入，先前的循环密钥和来自常量发生器的值来确定循环密钥的逻辑。常数发生器包括用于输出每个时钟周期的常数列表中的连续的一个的逻辑，并将输出的常数存储在存储单元中。存储单元的数量小于常量列表的大小。

10. 发明授权

US06828841B2 Clock receiver circuit for on-die salphasic clocking 失效
公开(公告)号：US06828841B2
公开(公告)日：2004-12-07
申请号：US10652668
申请日：2003-08-29
申请人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

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