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1. 发明授权

US06828841B2 Clock receiver circuit for on-die salphasic clocking 失效
公开(公告)号：US06828841B2
公开(公告)日：2004-12-07
申请号：US10652668
申请日：2003-08-29
申请人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

2. 发明授权

US06225826B1 Single ended domino compatible dual function generator circuits 失效
标题翻译：单端多米诺骨牌兼容双功能发生器电路
公开(公告)号：US06225826B1
公开(公告)日：2001-05-01
申请号：US09220816
申请日：1998-12-23
申请人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath , Mark A. Anders
发明人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath , Mark A. Anders
IPC分类号： H03K19096
CPC分类号： H03K19/096 , H03K19/0963
摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.
摘要翻译：在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态的中间信号。在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。

3. 发明授权

US06614279B2 Clock receiver circuit for on-die salphasic clocking 有权
标题翻译：时钟接收器电路，用于片上相关时钟
公开(公告)号：US06614279B2
公开(公告)日：2003-09-02
申请号：US09941457
申请日：2001-08-29
申请人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要翻译：时钟接收器电路将从差分时钟分配介质接收的低幅度差分时钟信号分量转换成全摆幅数字时钟。时钟接收器电路可以用作例如微电子器件内的管芯上的相关时钟分配系统的一部分。

4. 发明授权

US06204696B1 Domino circuits with high performance and high noise immunity 有权
标题翻译：具有高性能和高抗噪声能力的多米诺电路
公开(公告)号：US06204696B1
公开(公告)日：2001-03-20
申请号：US09158410
申请日：1998-09-22
申请人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal. In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower nFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal. In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor. An output stage includes an inverter to receive a signal from the domino stage conductor and to provide an evaluated output signal on an output conductor, the output stage including a duplicate evaluation path circuit coupled to an output conductor.
摘要翻译：在一些实施例中，本发明包括具有预充电电路的多米诺骨牌电路，该预充电电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。评估路径电路也耦合到多米诺骨牌导体。迟滞输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。在其他实施例中，本发明包括具有耦合到多米诺骨牌导体的预放电电路的多米诺骨牌电路。评估路径电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。滞后输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。在其他实施例中，本发明包括具有预充电电路的多米诺骨牌电路，其包括耦合到多米诺骨牌导体。评估路径电路耦合到多米诺骨牌导体。输出级包括反相器，用于从多米诺骨架导体接收信号并在输出导体上提供评估输出信号，输出级包括耦合到输出导体的重复评估路径电路。

5. 发明授权

US06617892B2 Single ended interconnect systems 失效
标题翻译：单端互连系统
公开(公告)号：US06617892B2
公开(公告)日：2003-09-09
申请号：US09157089
申请日：1998-09-18
申请人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03B100
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： In some embodiments, the invention includes an interconnect system having a single ended driver and a single ended hysteretic receiver. A single ended interconnect is coupled between the single ended driver and single ended receiver. In other embodiments, the invention involves an interconnect system including interconnects, single ended drivers, and single ended hysteretic receivers connected to respective ones of the interconnects. The single ended drivers receive respective data-in signals and an enable signal and wherein the drivers transmit interconnect signals on the interconnects when the enable signal is asserted. In yet other embodiments, the invention includes an interconnect system having interconnects, quasi-static drivers and receivers connected to respective ones of the interconnects. The quasi-static drivers to transmit interconnect signals on the interconnects, the quasi-static drivers receive a clock signal and respective data-in signals, and wherein the interconnect signals are pre-discharge when the clock signal changes from a first to a second state, and wherein when the clock signal is in the first state, the interconnect signals are related to the data-in signals. In still other embodiments, the invention includes a pseudo differential interconnect system and an interconnect system with a dual rail driver.
摘要翻译：在一些实施例中，本发明包括具有单端驱动器和单端滞后接收器的互连系统。单端互连连接在单端驱动器和单端接收器之间。在其他实施例中，本发明涉及一种互连系统，包括互连，单端驱动器和连接到相应的互连的单端滞后接收器。单端驱动器接收相应的数据输入信号和使能信号，并且其中当使能信号被断言时，驱动器在互连上发送互连信号。在其他实施例中，本发明包括具有互连的互连系统，准静态驱动器和连接到相应的互连的接收器。用于在互连上传输互连信号的准静态驱动器，准静态驱动器接收时钟信号和相应的数据输入信号，并且其中当时钟信号从第一状态变为第二状态时，互连信号是预放电的，并且其中当所述时钟信号处于所述第一状态时，所述互连信号与所述数据输入信号相关。在其他实施例中，本发明包括伪差分互连系统和具有双轨驱动器的互连系统。

6. 发明授权

US06838910B2 Fast dual-rail dynamic logic style 失效
标题翻译：快速双轨动态逻辑风格
公开(公告)号：US06838910B2
公开(公告)日：2005-01-04
申请号：US10633127
申请日：2003-08-01
申请人： Atila Alvandpour , Per Larsson-Edefors , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Atila Alvandpour , Per Larsson-Edefors , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K3/356113 , H03K3/356173
摘要： A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
摘要翻译：公开了一种具有自动切断机构的双轨静态逻辑门。在一个实施例中，第一轨道的输出耦合到第二轨道的上拉装置的输入端，反之亦然。交叉耦合允许静态门的自我截止机制正常工作，并提供具有比常规静态门更低的电容的组件。较低的电容导致更快的静态栅极。

7. 发明授权

US06717441B2 Flash [II]-Domino: a fast dual-rail dynamic logic style 失效
标题翻译： Flash [II] -Domino：快速双轨动态逻辑风格
公开(公告)号：US06717441B2
公开(公告)日：2004-04-06
申请号：US10021544
申请日：2001-10-22
申请人： Atila Alvandpour , Per Larsson-Edefors , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Atila Alvandpour , Per Larsson-Edefors , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03K19096
CPC分类号： H03K3/356113 , H03K3/356173
摘要： A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
摘要翻译：公开了一种具有自动切断机构的双轨静态逻辑门。在一个实施例中，第一轨道的输出耦合到第二轨道的上拉装置的输入端，反之亦然。交叉耦合允许静态门的自我截止机制正常工作，并提供具有比常规静态门更低的电容的组件。较低的电容导致更快的静态栅极。

8. 发明授权

US06549040B1 Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates 有权
标题翻译：具有双输出产生能力的漏电保护器，用于深亚微米宽多米诺骨门
公开(公告)号：US06549040B1
公开(公告)日：2003-04-15
申请号：US09608683
申请日：2000-06-29
申请人： Atila Alvandpour , Krishnamurthy Soumyanath , Ram K. Krishnamurthy
发明人： Atila Alvandpour , Krishnamurthy Soumyanath , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.
摘要翻译：一种电路，包括输入时钟信号以接收时钟信号，输入至少一个数据信号以接收至少一个数据信号，以及多输入条件反相器以接收时钟信号和数据信号，并产生动态输出。电路还包括条件保持器电路，用于在时钟评估和动态输出为高时为动态输出节点充电。

9. 发明授权

US07840885B2 Distributed ring control circuits for Viterbi traceback 有权
标题翻译：用于维特比回溯的分布式环形控制电路
公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
申请人： Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译：移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。

10. 发明授权

US07352209B2 Voltage-level converter 有权
标题翻译：电压电平转换器
公开(公告)号：US07352209B2
公开(公告)日：2008-04-01
申请号：US11411647
申请日：2006-04-26
申请人： Steven K. Hsu , Mark A. Anders , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Mark A. Anders , Ram K. Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
摘要翻译：电压电平转换器包括静态电压电平转换器和耦合到静态电压电平转换器的分离电平输出电路。在另一实施例中，电压电平转换器包括静态电压电平转换器，第一晶体管和第二晶体管。静态电压电平转换器包括输入节点，第一上拉节点，第二上拉节点，逆变器输出节点和输出节点。第一晶体管耦合到输入节点和第一上拉节点。第二晶体管耦合到第二上拉节点和逆变器输出节点。

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