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1. 发明授权

US07352209B2 Voltage-level converter 有权
标题翻译：电压电平转换器
公开(公告)号：US07352209B2
公开(公告)日：2008-04-01
申请号：US11411647
申请日：2006-04-26
申请人： Steven K. Hsu , Mark A. Anders , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Mark A. Anders , Ram K. Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
摘要翻译：电压电平转换器包括静态电压电平转换器和耦合到静态电压电平转换器的分离电平输出电路。在另一实施例中，电压电平转换器包括静态电压电平转换器，第一晶体管和第二晶体管。静态电压电平转换器包括输入节点，第一上拉节点，第二上拉节点，逆变器输出节点和输出节点。第一晶体管耦合到输入节点和第一上拉节点。第二晶体管耦合到第二上拉节点和逆变器输出节点。

2. 发明授权

US07272029B2 Transition-encoder sense amplifier 有权
标题翻译：转换编码器读出放大器
公开(公告)号：US07272029B2
公开(公告)日：2007-09-18
申请号：US11025778
申请日：2004-12-29
申请人： Steven K. Hsu , Ram K. Krishnamurthy , Mark A. Anders
发明人： Steven K. Hsu , Ram K. Krishnamurthy , Mark A. Anders
IPC分类号： G11C11/00
CPC分类号： G11C7/08 , G11C7/065
摘要： A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
摘要翻译：读出放大器转换将输出信号编码到总线上，使得当感测到的位线具有与先前感测的位线的状态不同的状态时，总线信号仅转变。读出放大器包括当总线信号被断言时改变状态的存储元件。基于存储元件的状态，读出放大器的输出有条件地反转。

3. 发明授权

US06628143B2 Full-swing source-follower leakage tolerant dynamic logic 有权
标题翻译：全摆动源跟踪器泄漏容错动态逻辑
公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
申请人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译：全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。

4. 发明授权

US07606062B2 Ultra low voltage and minimum operating voltage tolerant register file 有权
标题翻译：超低电压和最低工作电压容限寄存器文件
公开(公告)号：US07606062B2
公开(公告)日：2009-10-20
申请号：US12006238
申请日：2007-12-31
申请人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
摘要翻译：描述了关于超低电压存储器位单元的方法和装置。在一个实施例中，使用对由互补写入字线控制的数据存储节点的冗余路径提供超低电压存储器件。还描述了其它实施例。

5. 发明申请

US20090085637A1 Apparatus effecting interface between differing signal levels 审中-公开
标题翻译：影响不同信号电平之间接口的设备
公开(公告)号：US20090085637A1
公开(公告)日：2009-04-02
申请号：US11906166
申请日：2007-09-28
申请人： Steven K. Hsu , Himanshu Kaul , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Himanshu Kaul , Ram K. Krishnamurthy
IPC分类号： H03L5/00
CPC分类号： H03K19/0175 , H03K3/356139
摘要： An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value.
摘要翻译：一种装置包括：信号接收单元，接收输入信号并呈现在第一信号范围内变化的第一信号; 与所述信号接收单元耦合的信号处理单元，接收所述第一信号并呈现在第二信号范围内变化的第二信号; 以及与信号处理单元耦合的输出单元。信号处理单元和输出单元接收控制信号。当控制信号具有第一值时，信号处理单元响应控制信号以向输出单元提供第二信号，并且当控制信号具有第二值时，信号处理单元不向输出单元提供第二信号。当控制信号具有第一值时，输出单元允许呈现输出信号，并且当控制信号具有第二值时，输出单元确定输出信号为预定值。

6. 发明授权

US06762957B2 Low clock swing latch for dual-supply voltage design 有权
标题翻译：低电压时钟摆动锁存器用于双电源电压设计
公开(公告)号：US06762957B2
公开(公告)日：2004-07-13
申请号：US10027795
申请日：2001-12-20
申请人： Steven K. Hsu , Bhaskar P. Chatterjee , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Bhaskar P. Chatterjee , Ram K. Krishnamurthy
IPC分类号： G11C710
CPC分类号： H03K3/356139 , H03K3/012
摘要： A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.
摘要翻译：双电源电压锁存器包括用于接收输入数据的数据输入节点，用于保存输入数据的内部节点以及输出输出数据的输出节点。锁存器还包括时钟输入节点以接收时钟信号。数据输入，内部和数据输出节点处于比时钟节点更高的电位。由于时钟节点是高活动节点，所以这些节点上的较小电位降低了锁存器消耗的能量。虽然数据节点和时钟节点处于不同的电位，但锁存器降低了静态功耗。

7. 发明授权

US07855575B1 Wide voltage range level shifter with symmetrical switching 有权
标题翻译：具有对称开关的宽电压范围电平移位器
公开(公告)号：US07855575B1
公开(公告)日：2010-12-21
申请号：US12566977
申请日：2009-09-25
申请人： Steven K. Hsu , Daniel I. Davis , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Daniel I. Davis , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： Described herein is the method and apparatus for generating symmetrical level shifted signals by a symmetrical level shifter. The symmetrical level shifter comprises an edge detector operable to generate transition edge based pulses from an input signal based on a first power supply level; a voltage level shifter, coupled with the edge detector, operable to convert the transition edge based pulses based on the first power supply level to edge based pulses based on a second power supply level; and a divider circuit, coupled with the voltage level shifter, operable to generate an output signal from the edge based pulses based on the second power supply level.
摘要翻译：这里描述了通过对称电平移位器产生对称电平移位信号的方法和装置。对称电平移位器包括边沿检测器，其可操作以基于第一电源电平从输入信号产生基于过渡沿的脉冲; 与边缘检测器耦合的电压电平移位器可操作以基于第二电源电平将基于第一电源电平的基于边沿的脉冲转换为基于边缘的脉冲; 以及与所述电压电平移位器耦合的分频器电路，用于基于所述第二电源电平从所述基于边沿的脉冲产生输出信号。

8. 发明授权

US07372763B2 Memory with spatially encoded data storage 有权
标题翻译：内存空间编码数据存储
公开(公告)号：US07372763B2
公开(公告)日：2008-05-13
申请号：US11321366
申请日：2005-12-28
申请人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1006 , G11C7/22 , G11C7/222 , G11C2207/2227
摘要： In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written to a portion of the memory circuit. The majority voter circuit determines if the data bits are to be inverted prior to being written into the memory circuit portion.
摘要翻译：在一些实施例中，本发明提供具有至少一个存储器电路的芯片，该存储器电路包括具有第一和第二数字控制的可变延迟元件的多数选举电路。第一延迟元件由要被写入存储器电路的一部分的数据位控制。大多数选择电路确定在写入存储器电路部分之前数据比特是否被反转。

9. 发明授权

US07132856B2 Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors 有权
公开(公告)号：US07132856B2
公开(公告)日：2006-11-07
申请号：US10924906
申请日：2004-08-25
申请人： Steven K. Hsu , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Ram K. Krishnamurthy
IPC分类号： H03K19/0175 , H03K19/096 , H03K3/017 , H03K3/356
CPC分类号： H03K3/356156
摘要： A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and second stage storage circuits are driven with a first supply voltage and an inverter coupled to the first stage storage circuit is driven with a second supply voltage. In either case, data transfer into the storage circuits may be controlled by different states of a clock signal. The logic circuit may be a flip-flop circuit, a latch circuit, or another type of circuit.

10. 发明授权

US06707708B1 Static random access memory with symmetric leakage-compensated bit line 失效
标题翻译：具有对称泄漏补偿位线的静态随机存取存储器
公开(公告)号：US06707708B1
公开(公告)日：2004-03-16
申请号：US10241791
申请日：2002-09-10
申请人： Atila Alvandpour , Dinesh Somasekhar , Steven K. Hsu , Ram K. Krishnamurthy , Vivek K. De
发明人： Atila Alvandpour , Dinesh Somasekhar , Steven K. Hsu , Ram K. Krishnamurthy , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412 , G11C11/419
摘要： An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.
摘要翻译：用于静态随机存取存储器的八单元，存储单元包括用于存储信息位的交叉耦合反相器，连接到局部位线的两个存取nMOSFET以访问所存储的信息位，以及两个nMOSFET，每个具有连接到地的栅极和耦合到本地位线和交叉耦合的反相器，使得到达和从本地位线到不被读取的存储器单元的子阈值泄漏电流被平衡。

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