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1. 发明授权

US06562724B1 Self-aligned stack formation 失效
标题翻译：自对齐堆叠形成
公开(公告)号：US06562724B1
公开(公告)日：2003-05-13
申请号：US09089795
申请日：1998-06-03
申请人： Steve Hsia , Yin Hu
发明人： Steve Hsia , Yin Hu
IPC分类号： H01L21302
CPC分类号： H01L29/66583 , H01L21/28061 , H01L21/31116 , H01L21/32136 , H01L29/4933
摘要： A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and then using the silicide 260 to mask removal of the unreacted silicon 220 and 230 in locations where the hardmask 240 had been present. The metal silicide 260 formed in the exposed silicon regions 220 and 230 functions as a self-aligned mask against the silicon 220 and 230 etching. By using a selective etching process between the silicon 220 and 230 and the silicide 260, the silicon 220 and 230 can be etched down to the gate oxide 210 to form the polycide (silicide/polysilicon) gate. The polycide gate formed by this method is particularly advantageous in DRAM applications, but can also be used as a MOS gate in a transistor.
摘要翻译：一种通过使用硬掩模240来限定硅化层260的图案来硅化硅层230来简化多晶硅栅极结构制造工艺的方法，然后使用硅化物260掩盖在硬掩模240具有的位置处的未反应硅220和230的去除已经存在形成在暴露的硅区域220和230中的金属硅化物260用作抵抗硅220和230蚀刻的自对准掩模。通过在硅220和230与硅化物260之间使用选择性蚀刻工艺，可将硅220和230蚀刻到栅极氧化物210以形成多晶硅化物（硅化物/多晶硅）栅极。通过该方法形成的多晶硅栅极在DRAM应用中特别有利，但也可以用作晶体管中的MOS栅极。

2. 发明申请

US20060245243A1 Multi-resistive state element with reactive metal 有权
公开(公告)号：US20060245243A1
公开(公告)日：2006-11-02
申请号：US11473005
申请日：2006-06-22
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Hsia , Steven Longcor , Christophe Chevallier , John Sanchez , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Hsia , Steven Longcor , Christophe Chevallier , John Sanchez , Philip Swab
IPC分类号： G11C11/14
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

3. 发明申请

US20050101086A1 CONDUCTIVE MEMORY STACK WITH NON-UNIFORM WIDTH 有权
标题翻译：具有非均匀宽度的导电记忆层
公开(公告)号：US20050101086A1
公开(公告)日：2005-05-12
申请号：US10605963
申请日：2003-11-10
申请人： Darrell Rinerson , Steve Hsia , Steven Longcor , Wayne Kinney , Edmond Ward , Christophe Chevallier
发明人： Darrell Rinerson , Steve Hsia , Steven Longcor , Wayne Kinney , Edmond Ward , Christophe Chevallier
IPC分类号： G11C11/56 , G11C13/00 , H01L21/8246 , H01L27/115 , H01L41/24 , H01L21/336
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.
摘要翻译：提供导电存储器堆叠。存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面第四表面积。多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。此外，第四表面积不等于第二表面积。

4. 发明申请

US20050013172A1 Multiple modes of operation in a cross point array 有权
公开(公告)号：US20050013172A1
公开(公告)日：2005-01-20
申请号：US10921037
申请日：2004-08-17
申请人： Darrell Rinerson , Christophe Chevallier , Steven Longcor , Edmond Ward , Wayne Kinney , Steve Hsia
发明人： Darrell Rinerson , Christophe Chevallier , Steven Longcor , Edmond Ward , Wayne Kinney , Steve Hsia
IPC分类号： G11C11/56 , G11C13/00 , G11C8/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a first level and indicative of a second program state when the read current is at a second level. The read current is ineffective to produce a change in program state. A first voltage pulse is used during a first write mode if a change from a second program state to a first program state is desired. A second voltage pulse is used during a second write mode if a change from the first program state to the second program state is desired.

5. 发明申请

US20070158716A1 Conductive memory stack with sidewall 有权
公开(公告)号：US20070158716A1
公开(公告)日：2007-07-12
申请号：US11714555
申请日：2007-03-05
申请人： Darrell Rinerson , Steve Hsia , Steven Longcor , Wayne Kinney , Edmond Ward , Christophe Chevallier
发明人： Darrell Rinerson , Steve Hsia , Steven Longcor , Wayne Kinney , Edmond Ward , Christophe Chevallier
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

6. 发明授权

US5969397A Low defect density composite dielectric 失效
标题翻译：低缺陷密度复合电介质
公开(公告)号：US5969397A
公开(公告)日：1999-10-19
申请号：US974325
申请日：1997-11-19
申请人： Douglas Ticknor Grider, III , Paul Edward Nicollian , Steve Hsia
发明人： Douglas Ticknor Grider, III , Paul Edward Nicollian , Steve Hsia
IPC分类号： H01L29/78 , H01L21/28 , H01L21/314 , H01L21/318 , H01L29/51 , H01L29/76 , H01L29/94
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A composite dielectric layer (102). A first layer (112) of the composite dielectric layer (102) has a small to no nitrogen concentration. A second layer (114) of the composite dielectric layer (102) has a larger nitrogen concentration (e.g., 5-15%). The composite dielectric layer (102) may be used as a thin gate dielectric wherein the second layer (114) is located adjacent a doped gate electrode (110) and has sufficient nitrogen concentration to stop penetration of dopant from the gate electrode (110) to the channel region (108). The first layer (112) is located between the second layer (114) and the channel region (108). The low nitrogen concentration of the first layer (112) is limited so as to not interfere with carrier mobility in the channel region (108).
摘要翻译：复合电介质层（102）。复合介电层（102）的第一层（112）具有小至无氮浓度。复合介电层（102）的第二层（114）具有较大的氮浓度（例如5-15％）。复合介电层（102）可以用作薄栅极电介质，其中第二层（114）位于掺杂栅电极（110）附近，并且具有足够的氮浓度以阻止掺杂剂从栅电极（110）穿透至通道区域（108）。第一层（112）位于第二层（114）和沟道区（108）之间。限制第一层（112）的低氮浓度，以便不干扰通道区域（108）中的载流子迁移率。

7. 发明授权

US4577391A Method of manufacturing CMOS devices 失效
标题翻译：制造CMOS器件的方法
公开(公告)号：US4577391A
公开(公告)日：1986-03-25
申请号：US635371
申请日：1984-07-27
申请人： Steve Hsia , Paul Chang
发明人： Steve Hsia , Paul Chang
IPC分类号： H01L27/092 , H01L21/265 , H01L21/8238 , H01L29/78 , H01L21/32
CPC分类号： H01L21/823864
摘要： A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.
摘要翻译：具有绝缘侧壁间隔物的CMOS半导体结构，其宽度针对NMOS和PMOS器件独立选择。选择间隔物的宽度以减少N沟道器件中的热电子注入，并确保栅极和源极区域与P沟道器件中的栅极对准或下划线。对于P沟道器件使用较窄的间隔物，而不是N沟道器件，其允许形成阈值电压小于1伏特的P沟道器件。

8. 发明申请

US20050243595A1 MEMORY ELEMENT HAVING ISLANDS 有权
标题翻译：有岛屿的记忆元素
公开(公告)号：US20050243595A1
公开(公告)日：2005-11-03
申请号：US10868578
申请日：2004-06-15
申请人： Darrell Rinerson , Christophe Chevallier , Philip Swab , Steve Hsia , John Sanchez , Mary Calarrudo , Steven Longcor , Wayne Kinney
发明人： Darrell Rinerson , Christophe Chevallier , Philip Swab , Steve Hsia , John Sanchez , Mary Calarrudo , Steven Longcor , Wayne Kinney
IPC分类号： G11C11/00 , G11C11/56 , G11C13/02
CPC分类号： G11C13/0011 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/77 , G11C2213/79
摘要： A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.
摘要翻译：提供了包括具有岛的存储元件的存储器。存储器具有地址解码电路和一组存储器插头。存储器插头包括在第二材料的主体内具有第一材料的岛结构的存储元件。岛结构通常是纳米颗粒。存储器插头可以以第一写入电压处于第一电阻状态，以第二写入电压置于第二电阻状态，并且在读取电压下确定其电阻状态。

9. 发明申请

US20050174835A1 Multi-resistive state element with reactive metal 有权
标题翻译：具有反应性金属的多电阻状态元件
公开(公告)号：US20050174835A1
公开(公告)日：2005-08-11
申请号：US10773549
申请日：2004-02-06
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Hsia , Steven Longcor , Christophe Chevallier , John Sanchez , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Hsia , Steven Longcor , Christophe Chevallier , John Sanchez , Philip Swab
IPC分类号： G11C11/16 , G11C11/56 , G11C13/00 , H01L27/24 , G11C11/14
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译：提供经处理的导电元件。可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。该结构还具有非线性IV特性，这在某些阵列中是有利的。

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