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1. 发明授权

US5969397A Low defect density composite dielectric 失效
标题翻译：低缺陷密度复合电介质
公开(公告)号：US5969397A
公开(公告)日：1999-10-19
申请号：US974325
申请日：1997-11-19
申请人： Douglas Ticknor Grider, III , Paul Edward Nicollian , Steve Hsia
发明人： Douglas Ticknor Grider, III , Paul Edward Nicollian , Steve Hsia
IPC分类号： H01L29/78 , H01L21/28 , H01L21/314 , H01L21/318 , H01L29/51 , H01L29/76 , H01L29/94
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A composite dielectric layer (102). A first layer (112) of the composite dielectric layer (102) has a small to no nitrogen concentration. A second layer (114) of the composite dielectric layer (102) has a larger nitrogen concentration (e.g., 5-15%). The composite dielectric layer (102) may be used as a thin gate dielectric wherein the second layer (114) is located adjacent a doped gate electrode (110) and has sufficient nitrogen concentration to stop penetration of dopant from the gate electrode (110) to the channel region (108). The first layer (112) is located between the second layer (114) and the channel region (108). The low nitrogen concentration of the first layer (112) is limited so as to not interfere with carrier mobility in the channel region (108).
摘要翻译：复合电介质层（102）。复合介电层（102）的第一层（112）具有小至无氮浓度。复合介电层（102）的第二层（114）具有较大的氮浓度（例如5-15％）。复合介电层（102）可以用作薄栅极电介质，其中第二层（114）位于掺杂栅电极（110）附近，并且具有足够的氮浓度以阻止掺杂剂从栅电极（110）穿透至通道区域（108）。第一层（112）位于第二层（114）和沟道区（108）之间。限制第一层（112）的低氮浓度，以便不干扰通道区域（108）中的载流子迁移率。

2. 发明授权

US07737717B2 Current-voltage-based method for evaluating thin dielectrics based on interface traps 有权
标题翻译：基于电流电压的方法，用于评估基于界面陷阱的薄电介质
公开(公告)号：US07737717B2
公开(公告)日：2010-06-15
申请号：US12209986
申请日：2008-09-12
申请人： Paul Edward Nicollian , Anand T. Krishnan , Vijay K. Reddy
发明人： Paul Edward Nicollian , Anand T. Krishnan , Vijay K. Reddy
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2648 , G01R31/2858 , H01L22/34
摘要： A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t). Following the stressing, post-stress I-V testing is performed (104) wherein the first, second and third measurements are repeated to obtain post-stress I-V test data. The gate dielectric is evaluated (105) from the pre-stress and post-stress I-V test data.
摘要翻译：一种用于评估栅极电介质（100）的方法包括提供测试结构（101）。测试结构包括栅极堆叠，其包括在衬底上的栅极电介质上的栅极电极，以及扩散在衬底中的至少一个扩散区域，其包括栅极堆叠下方的部分和超过栅极堆叠的部分。在测试结构上执行预应力离态IV测试（102）以获得预应力IV测试数据，其中预应力截止状态IV测试包括涉及栅电极，衬底和扩散的第一测量区域，涉及所述栅电极和所述扩散区域的衬底浮动的第二测量，以及涉及所述栅电极和所述扩散区域的第三测量，所述衬底浮置。然后将测试结构应力（103）包括电应力一段时间（t）。在应力之后，执行后应力I-V测试（104），其中重复第一，第二和第三测量以获得后应力I-V测试数据。从预应力和后应力I-V测试数据评估栅极电介质（105）。

3. 发明申请

US20090224795A1 CURRENT-VOLTAGE-BASED METHOD FOR EVALUATING THIN DIELECTRICS BASED ON INTERFACE TRAPS 有权
标题翻译：基于电流传导的电流评估方法
公开(公告)号：US20090224795A1
公开(公告)日：2009-09-10
申请号：US12209986
申请日：2008-09-12
申请人： Paul Edward Nicollian , Anand T. Krishnan , Vijay K. Reddy
发明人： Paul Edward Nicollian , Anand T. Krishnan , Vijay K. Reddy
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2648 , G01R31/2858 , H01L22/34
摘要： A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t). Following the stressing, post-stress I-V testing is performed (104) wherein the first, second and third measurements are repeated to obtain post-stress I-V test data. The gate dielectric is evaluated (105) from the pre-stress and post-stress I-V test data.
摘要翻译：一种用于评估栅极电介质（100）的方法包括提供测试结构（101）。测试结构包括栅极堆叠，其包括在衬底上的栅极电介质上的栅极电极，以及扩散在衬底中的至少一个扩散区域，其包括栅极堆叠下方的部分和超过栅极堆叠的部分。在测试结构上执行预应力关闭状态IV测试（102）以获得预应力IV测试数据，其中预应力off-state IV测试包括涉及栅电极，衬底和扩散的第一测量区域，涉及所述栅电极和所述扩散区域的衬底浮动的第二测量，以及涉及所述栅电极和所述扩散区域的第三测量，所述衬底浮置。然后将测试结构应力（103）包括电应力一段时间（t）。在应力之后，执行后应力I-V测试（104），其中重复第一，第二和第三测量以获得后应力I-V测试数据。从预应力和后应力I-V测试数据评估栅极电介质（105）。

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