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1. 发明授权

US08530337B1 Method of large-area circuit layout recognition 有权
公开(公告)号：US08530337B1
公开(公告)日：2013-09-10
申请号：US13530605
申请日：2012-06-22
申请人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , John A. Ott , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , John A. Ott , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L21/304
CPC分类号： H01L22/12 , H01L21/304 , H01L21/7806 , H01L21/7813
摘要： Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

2. 发明授权

US08592323B1 Method of large-area circuit layout recognition 失效
公开(公告)号：US08592323B1
公开(公告)日：2013-11-26
申请号：US13555261
申请日：2012-07-23
申请人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , John A. Ott , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , John A. Ott , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L21/469
CPC分类号： H01L22/12 , H01L21/304 , H01L21/7806 , H01L21/7813
摘要： Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

3. 发明授权

US07705345B2 High performance strained silicon FinFETs device and method for forming same 有权
标题翻译：高性能应变硅FinFET器件及其形成方法
公开(公告)号：US07705345B2
公开(公告)日：2010-04-27
申请号：US10751916
申请日：2004-01-07
申请人： Stephen W. Bedell , Kevin K. Chan , Dureseti Chidambarrao , Silke H. Christianson , Jack O. Chu , Anthony G. Domenicucci , Kam-Leung Lee , Anda C. Mocuta , John A. Ott , Qiqing C. Ouyang
发明人： Stephen W. Bedell , Kevin K. Chan , Dureseti Chidambarrao , Silke H. Christianson , Jack O. Chu , Anthony G. Domenicucci , Kam-Leung Lee , Anda C. Mocuta , John A. Ott , Qiqing C. Ouyang
IPC分类号： H01L29/06 , H01L31/072
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.
摘要翻译：应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。松弛的第一材料和应变的第二材料形成FinFET的鳍。

4. 发明申请

US20120190155A1 NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN 审中-公开
标题翻译： NONOWIRE MOSFET，具有用于源和漏极的外延接头
公开(公告)号：US20120190155A1
公开(公告)日：2012-07-26
申请号：US13440590
申请日：2012-04-05
申请人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
发明人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/458 , H01L29/7839 , H01L29/785 , H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要翻译：公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。讨论了顶盖门控和底部门控纳米线FET结构。源极和漏极制造可以使用选择性或非选择性外延。

5. 发明授权

US08138061B2 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide 有权
标题翻译：使用亲水硅表面的准疏水Si-Si晶片结合和界面结合氧化物的溶解
公开(公告)号：US08138061B2
公开(公告)日：2012-03-20
申请号：US11031165
申请日：2005-01-07
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/46
CPC分类号： H01L21/187 , H01L21/76251
摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.
摘要翻译：本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与用疏水性接合实现的特性相当的性质的结合Si-Si界面的方法。约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

6. 发明授权

US08053330B2 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide 有权
标题翻译：使用亲水硅表面的准疏水Si-Si晶片结合和界面结合氧化物的溶解
公开(公告)号：US08053330B2
公开(公告)日：2011-11-08
申请号：US12538115
申请日：2009-08-08
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/46
CPC分类号： H01L21/187 , H01L21/76251
摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.
摘要翻译：本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与通过疏水性接合实现的性能相当的特性的结合Si-Si界面的方法。约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

7. 发明授权

US07999251B2 Nanowire MOSFET with doped epitaxial contacts for source and drain 有权
标题翻译：具有用于源极和漏极的掺杂外延触点的纳米线MOSFET
公开(公告)号：US07999251B2
公开(公告)日：2011-08-16
申请号：US11519176
申请日：2006-09-11
申请人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
发明人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
IPC分类号： H01L29/775 , H01L29/786
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/458 , H01L29/7839 , H01L29/785 , H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要翻译：公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。讨论了顶盖门控和底部门控纳米线FET结构。源极和漏极制造可以使用选择性或非选择性外延。

8. 发明授权

US06858502B2 High speed composite p-channel Si/SiGe heterostructure for field effect devices 失效
标题翻译：用于场效应器件的高速复合p沟道Si / SiGe异质结构
公开(公告)号：US06858502B2
公开(公告)日：2005-02-22
申请号：US09989770
申请日：2001-11-20
申请人： Jack Oon Chu , Richard Hammond , Khalid EzzEldin Ismail , Steven John Koester , Patricia May Mooney , John A. Ott
发明人： Jack Oon Chu , Richard Hammond , Khalid EzzEldin Ismail , Steven John Koester , Patricia May Mooney , John A. Ott
IPC分类号： H01L29/161 , H01L21/338 , H01L29/10 , H01L29/778 , H01L29/78 , H01L29/812 , H01L21/336
CPC分类号： H01L29/7782 , H01L29/1025 , H01L29/1054
摘要： A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
摘要翻译：一种用于形成p沟道场效应晶体管的方法和分层异质结构被描述为在半导体衬底上并入多个半导体层，第一外延Ge层的复合沟道结构和具有较高势垒的第二压缩应变SiGe层更深的约束量子阱并具有极高的空穴迁移率。本发明克服了仅具有单个压缩应变SiGe沟道层的p沟道器件的有限空穴迁移率的问题。

9. 发明申请

US20140024211A1 USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES 有权
公开(公告)号：US20140024211A1
公开(公告)日：2014-01-23
申请号：US13551962
申请日：2012-07-18
申请人： John A. Ott , Ageeth A. Bol
发明人： John A. Ott , Ageeth A. Bol
IPC分类号： H01L21/768
CPC分类号： H01L23/52 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L23/5222 , H01L23/53238 , H01L23/53276 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

10. 发明授权

US08610278B1 Use of graphene to limit copper surface oxidation, diffusion and electromigration in interconnect structures 有权
公开(公告)号：US08610278B1
公开(公告)日：2013-12-17
申请号：US13587521
申请日：2012-08-16
申请人： John A. Ott , Ageeth A. Bol
发明人： John A. Ott , Ageeth A. Bol
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/52 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L23/5222 , H01L23/53238 , H01L23/53276 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

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