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1. 发明授权

US5384737A Pipelined memory having synchronous and asynchronous operating modes 失效
标题翻译：流水线存储器具有同步和异步操作模式
公开(公告)号：US5384737A
公开(公告)日：1995-01-24
申请号：US207509
申请日：1994-03-08
申请人： Lawrence F. Childs , Kenneth W. Jones , Stephen T. Flannagan , Ray Chang
发明人： Lawrence F. Childs , Kenneth W. Jones , Stephen T. Flannagan , Ray Chang
IPC分类号： G11C7/10 , G11C29/14 , G11C13/00
CPC分类号： G11C29/14 , G11C7/1039 , G11C7/1045 , G11C7/1072
摘要： A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).
摘要翻译：流水线存储器（20）具有同步操作模式和异步操作模式。存储器（20）包括用于在异步操作模式和同步操作模式之间电切换的输出寄存器（34）和输出使能寄存器（48）。另外，在同步运行模式中，流水线的深度可以在三段管线和两级管线之间变化。通过改变流水线的深度，存储器（20）可以使用更大的时钟频率范围来操作。另外，可以改变操作频率以便于存储器（20）的测试和调试。

2. 发明授权

US5440514A Write control for a memory using a delay locked loop 失效
标题翻译：使用延迟锁定环对内存进行写入控制
公开(公告)号：US5440514A
公开(公告)日：1995-08-08
申请号：US207510
申请日：1994-03-08
申请人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
发明人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
IPC分类号： G11C7/22 , G11C17/10
CPC分类号： G11C7/222 , G11C7/22
摘要： A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.
摘要翻译：存储器（20）包括用于控制存储器（20）的写周期的写控制延迟锁定环（52）。延迟锁定环（52）包括仲裁电路（264），电压控制延迟（VCD）电路（260）和VCD控制电路（265）。仲裁器电路（264）将时钟信号与来自VCD电路（260）的延迟的时钟信号进行比较。作为响应，仲裁器电路（264）向VCD控制电路（265）提供延迟信号。 VCD控制电路（265）接收延迟信号并调整延迟的时钟信号的传播延迟以补偿时钟频率的变化，以及补偿处理，温度和电源变化。

3. 发明授权

US5670815A Layout for noise reduction on a reference voltage 失效
标题翻译：参考电压降噪布局
公开(公告)号：US5670815A
公开(公告)日：1997-09-23
申请号：US270560
申请日：1994-07-05
申请人： Lawrence F. Childs , Stephen T. Flannagan , Ray Chang , Donovan L. Raatz
发明人： Lawrence F. Childs , Stephen T. Flannagan , Ray Chang , Donovan L. Raatz
IPC分类号： H01L23/528 , H01L29/76 , H01L31/062
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V.sub.DD power supply lines (26, 30) for a first predetermined length, for providing capacitive coupling between V.sub.DD and a reference voltage. In the second portion (55), the reference voltage line (27) is disposed between two V.sub.SS power supply lines (28, 41) for a second predetermined length, for providing capacitive coupling between V.sub.SS and the reference voltage. The capacitive coupling stabilizes the reference voltage with respect to the power supply voltage, and reduces power supply noise due to lead inductance and changing current demand. In addition, the power supply lines (26, 28, 30, 41) are disposed half above an N-type region (22) and half above a P-type substrate (21) for reducing local transistor switching noise.
摘要翻译：布局部分（20）具有第一部分（25）和第二部分（55）。在第一部分（25）中，在两个VDD电源线（26,30）之间以第一预定长度设置参考电压线（27），用于在VDD和参考电压之间提供电容耦合。在第二部分（55）中，参考电压线（27）被设置在两个VSS电源线（28,41）之间的第二预定长度上，用于提供VSS与参考电压之间的电容耦合。电容耦合使参考电压相对于电源电压稳定，并且由于引线电感和电流需求的变化而降低了电源噪声。此外，电源线（26,28,30,41）在N型区域（22）的上方设置一半，并且在P型衬底（21）的上方设置一半以减少局部晶体管开关噪声。

4. 发明授权

US5440515A Delay locked loop for detecting the phase difference of two signals having different frequencies 失效
标题翻译：用于检测具有不同频率的两个信号的相位差的延迟锁定环
公开(公告)号：US5440515A
公开(公告)日：1995-08-08
申请号：US207517
申请日：1994-03-08
申请人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
发明人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/22
摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.
摘要翻译：延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步，。塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

5. 发明授权

US6157583A Integrated circuit memory having a fuse detect circuit and method therefor 有权
标题翻译：具有熔丝检测电路的集成电路存储器及其方法
公开(公告)号：US6157583A
公开(公告)日：2000-12-05
申请号：US261876
申请日：1999-03-02
申请人： Glenn E. Starnes , Stephen T. Flannagan , Ray Chang
发明人： Glenn E. Starnes , Stephen T. Flannagan , Ray Chang
IPC分类号： H01L21/82 , G06F11/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C7/00
CPC分类号： G11C29/02 , G06F11/006 , G11C29/44
摘要： Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.
摘要翻译：集成电路存储器（100）中的保险丝和检测电路（124）包括用于检测保险丝（208）的开路状态或闭路状态的铜熔丝（208）和熔丝状态检测级（202）。保险丝检测电路（124）提供对应于熔丝状态的输出信号，并且在检测期间，将熔丝两端的电压降限制为与施加到集成电路存储器的电源电压无关的绝对值。保险丝检测电路（124）在集成电路存储器（100）上电时工作，并且在保险丝的状态被检测和锁存之后被禁用，并且电源足以用于集成电路存储器（100）的可靠运行，。通过限制熔断的铜熔丝（208）上的电压降，潜在的电迁移问题就会降低。

6. 发明授权

US5610543A Delay locked loop for detecting the phase difference of two signals having different frequencies 失效
标题翻译：用于检测具有不同频率的两个信号的相位差的延迟锁定环
公开(公告)号：US5610543A
公开(公告)日：1997-03-11
申请号：US417155
申请日：1995-04-04
申请人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
发明人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
IPC分类号： G11C7/22 , H03L7/06 , H03K5/13
CPC分类号： G11C7/22
摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.
摘要翻译：延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步，。塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

7. 发明授权

US5477176A Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory 失效
标题翻译：上电复位电路，用于在集成电路存储器上电期间防止多个字线选择
公开(公告)号：US5477176A
公开(公告)日：1995-12-19
申请号：US253076
申请日：1994-06-02
申请人： Ray Chang , Lawrence F. Childs , Kenneth W. Jones , Donovan Raatz , Stephen Flannagan
发明人： Ray Chang , Lawrence F. Childs , Kenneth W. Jones , Donovan Raatz , Stephen Flannagan
IPC分类号： G11C11/413 , G11C5/14 , G11C8/10 , H03K17/22 , H03L7/00
CPC分类号： H03K17/223 , G11C5/143 , G11C8/10 , H03K17/22 , H03K2017/226
摘要： A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.
摘要翻译：用于存储器（20）的上电复位电路（30）包括DC模型电路（39），NBIAS校验电路（64）和NAND逻辑门（71）。在存储器（20）的上电时提供逻辑低电源复位信号，以在时钟电路（29）和行和列预解码器/锁存器（24,27）中建立初始条件。当电源电压，带隙参考电压和偏置电压都达到其预定电压时，上电复位电路（30）提供逻辑高的上电复位信号。以这种方式，确保上电复位电路（30）提供逻辑低功率复位信号，直到达到所有适当的电压电平。此外，上电复位电路为等效于地址缓冲电路（79）的DC电路建模，用于补偿过程和温度变化。

8. 发明申请

US20090100275A1 Dynamic port power allocation apparatus and methods 有权
标题翻译：动态端口功率分配设备及方法
公开(公告)号：US20090100275A1
公开(公告)日：2009-04-16
申请号：US11974699
申请日：2007-10-15
申请人： Ray Chang , David Ferguson
发明人： Ray Chang , David Ferguson
IPC分类号： G06F1/26
CPC分类号： H02J7/007 , G06F1/266 , H02J7/0052 , Y10T307/406
摘要： Methods and apparatus for dynamically adjusting the amount of power (or current) distributed to one or more connected devices via electrical interfaces. In one embodiment, the apparatus comprises a first module adapted to detect current drawn by a first set of ports, and a second module adapted to adjust the current provided to a second set of ports based on the detected current. The second module is also optionally adapted to distribute unreserved current among the devices according to an allocation protocol. In the exemplary context of a plurality of interconnected serial bus devices, the invention enables a device to draw more current than that required to be reserved for that device (such as to comply with a specification such as USB), yet without increasing the total amount of power which must be dedicated to the serial ports as a whole. Power supply efficiency may also be advantageously optimized.
摘要翻译：用于通过电接口动态调整分配给一个或多个连接设备的功率（或电流）量的方法和装置。在一个实施例中，该装置包括适于检测由第一组端口抽取的电流的第一模块，以及适于基于检测到的电流来调整提供给第二组端口的电流的第二模块。第二模块还可选地适于根据分配协议在设备之间分配未保留的电流。在多个互连的串行总线设备的示例性上下文中，本发明使得设备能够比不需要为该设备保留的电流（例如符合诸如USB的规范）绘制更多的电流，而不增加总量必须专门用于整个串行端口的电源。还可以有利地优化电源效率。

9. 发明授权

US07306487B1 Low crosstalk transmission connector 失效
标题翻译：低串扰传输连接器
公开(公告)号：US07306487B1
公开(公告)日：2007-12-11
申请号：US11594243
申请日：2006-11-08
申请人： Ray Chang
发明人： Ray Chang
IPC分类号： H01R13/648
CPC分类号： H01R13/6461 , H01R13/6474 , H01R13/6593 , H01R24/64
摘要： A low crosstalk transmission connector includes a housing that houses a metal spring plate, a load bar, a terminal module and a locating frame, a cable organizer, which has an axle hole that receives a 8-wire cable and 8 wire grooves that separate the 8 insulated wires of the cable, and a metal shield that accommodates the cable organizer and has a bottom clamping plate and a top clamping plate respectively hooked on the bottom and top sides of the housing to ensure high steadity. The 4th and 6th metal contact terminals and the 1st, 2nd, 3rd, 5th, 7th and 8th metal contact terminals of the terminal module have the respective front contact portions curved in two reversed directions to reduce crosstalk noise, thereby improving transmission quality.
摘要翻译：低串扰传输连接器包括容纳金属弹簧板，负载杆，端子模块和定位框架的壳体，电缆组织器，其具有容纳8线电缆的轴孔和8条线槽，电缆的8根绝缘电线，以及容纳电缆组织器的金属屏蔽，并具有分别钩在外壳底部和顶部的底部夹紧板和顶部夹紧板，以确保高稳定性。第4和第6和/或第4金属接触端子以及第1，第2，第3，第3 端子模块的第<！ - SIPO - >第五，第七和/或第八/第五金属接触端子具有相应的前接触部分弯曲成两个反向方向以减少串扰噪声，从而提高传输质量。

10. 外观设计

USD553088S1 Toolless keystone connector 有权
标题翻译：无工具梯形连接器
公开(公告)号：USD553088S1
公开(公告)日：2007-10-16
申请号：US29232013
申请日：2005-06-15
申请人： Ray Chang
设计人： Ray Chang

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